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intel/fs/xe2+: Update TCS payload setup for Xe2 reg size.

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Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Francisco Jerez
2022-09-07 14:09:04 -07:00
committed by Jordan Justen
parent 6195eac210
commit 4b3243104c
1 changed files with 10 additions and 5 deletions
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15
src/intel/compiler/brw_fs_thread_payload.cpp
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@@ -57,16 +57,21 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
assert(tcs_key->input_vertices <= BRW_MAX_TCS_INPUT_VERTICES);
patch_urb_output = brw_ud8_grf(1, 0);
unsigned r = 0;
unsigned r = 2;
r += reg_unit(v.devinfo);
if (tcs_prog_data->include_primitive_id)
primitive_id = brw_vec8_grf(r++, 0);
patch_urb_output = brw_ud8_grf(r, 0);
r += reg_unit(v.devinfo);
if (tcs_prog_data->include_primitive_id) {
primitive_id = brw_vec8_grf(r, 0);
r += reg_unit(v.devinfo);
}
/* ICP handles occupy the next 1-32 registers. */
icp_handle_start = brw_ud8_grf(r, 0);
r += brw_tcs_prog_key_input_vertices(tcs_key);
r += brw_tcs_prog_key_input_vertices(tcs_key) * reg_unit(v.devinfo);
num_regs = r;
}