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anv/pipeline: Unify 3DSTATE_VS emission

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With this commit, a few fields are now specified on gen7 which weren't
before.  However, the values specified are zero which is the default so the
final hardware packet remains the same.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
This commit is contained in:
Jason Ekstrand
2016-11-12 08:43:54 -08:00
parent c3e908e9d3
commit 4a48d19d93
3 changed files with 89 additions and 82 deletions
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29
src/intel/vulkan/gen7_pipeline.c
View File

@@ -85,8 +85,6 @@ genX(graphics_pipeline_create)(
emit_ms_state(pipeline, pCreateInfo->pMultisampleState); emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
#if 0 #if 0
/* From gen7_vs_state.c */ /* From gen7_vs_state.c */
@@ -106,32 +104,7 @@ genX(graphics_pipeline_create)(
gen7_emit_vs_workaround_flush(brw); gen7_emit_vs_workaround_flush(brw);
#endif #endif
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX)); emit_3dstate_vs(pipeline);
const struct anv_shader_bin *vs_bin =
pipeline->shaders[MESA_SHADER_VERTEX];
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
vs.KernelStartPointer = vs_bin->kernel.offset;
vs.ScratchSpaceBasePointer = (struct anv_address) {
.bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
MESA_SHADER_VERTEX,
vs_prog_data->base.base.total_scratch),
.offset = 0,
};
vs.PerThreadScratchSpace = scratch_space(&vs_prog_data->base.base);
vs.DispatchGRFStartRegisterForURBData =
vs_prog_data->base.base.dispatch_grf_start_reg;
vs.SamplerCount = get_sampler_count(vs_bin);
vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin);
vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length;
vs.VertexURBEntryReadOffset = 0;
vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
vs.StatisticsEnable = true;
vs.FunctionEnable = true;
}
const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline); const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);

57
src/intel/vulkan/gen8_pipeline.c
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@@ -59,7 +59,6 @@ genX(graphics_pipeline_create)(
struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; struct anv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
struct anv_pipeline *pipeline; struct anv_pipeline *pipeline;
VkResult result; VkResult result;
uint32_t offset, length;
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO); assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
@@ -120,8 +119,8 @@ genX(graphics_pipeline_create)(
const struct anv_shader_bin *gs_bin = const struct anv_shader_bin *gs_bin =
pipeline->shaders[MESA_SHADER_GEOMETRY]; pipeline->shaders[MESA_SHADER_GEOMETRY];
offset = 1; uint32_t offset = 1;
length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset; uint32_t length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) { anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
gs.SingleProgramFlow = false; gs.SingleProgramFlow = false;
@@ -171,57 +170,7 @@ genX(graphics_pipeline_create)(
} }
} }
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline); emit_3dstate_vs(pipeline);
assert(!vs_prog_data->base.base.use_alt_mode);
/* Skip the VUE header and position slots */
offset = 1;
length = (vs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
const struct anv_shader_bin *vs_bin =
pipeline->shaders[MESA_SHADER_VERTEX];
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
vs.KernelStartPointer = vs_bin->kernel.offset;
vs.SingleVertexDispatch = false;
vs.VectorMaskEnable = false;
vs.SamplerCount = get_sampler_count(vs_bin);
vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin);
vs.ThreadDispatchPriority = false;
vs.FloatingPointMode = IEEE754;
vs.IllegalOpcodeExceptionEnable = false;
vs.AccessesUAV = false;
vs.SoftwareExceptionEnable = false;
vs.ScratchSpaceBasePointer = (struct anv_address) {
.bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
MESA_SHADER_VERTEX,
vs_prog_data->base.base.total_scratch),
.offset = 0,
};
vs.PerThreadScratchSpace = scratch_space(&vs_prog_data->base.base);
vs.DispatchGRFStartRegisterForURBData =
vs_prog_data->base.base.dispatch_grf_start_reg;
vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length;
vs.VertexURBEntryReadOffset = 0;
vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
vs.StatisticsEnable = true;
vs.SIMD8DispatchEnable =
vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
vs.VertexCacheDisable = false;
vs.FunctionEnable = true;
vs.VertexURBEntryOutputReadOffset = offset;
vs.VertexURBEntryOutputLength = length;
/* TODO */
vs.UserClipDistanceClipTestEnableBitmask = 0;
vs.UserClipDistanceCullTestEnableBitmask = 0;
}
const int num_thread_bias = GEN_GEN == 8 ? 2 : 1; const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) { if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {

85
src/intel/vulkan/genX_pipeline_util.h
View File

@@ -968,4 +968,89 @@ get_binding_table_entry_count(const struct anv_shader_bin *bin)
return DIV_ROUND_UP(bin->bind_map.surface_count, 32); return DIV_ROUND_UP(bin->bind_map.surface_count, 32);
} }
static inline struct anv_address
get_scratch_address(struct anv_pipeline *pipeline,
gl_shader_stage stage,
const struct anv_shader_bin *bin)
{
return (struct anv_address) {
.bo = anv_scratch_pool_alloc(pipeline->device,
&pipeline->device->scratch_pool,
stage, bin->prog_data->total_scratch),
.offset = 0,
};
}
static inline uint32_t
get_scratch_space(const struct anv_shader_bin *bin)
{
return ffs(bin->prog_data->total_scratch / 2048);
}
static inline uint32_t
get_urb_output_offset()
{
/* Skip the VUE header and position slots */
return 1;
}
static inline uint32_t
get_urb_output_length(const struct anv_shader_bin *bin)
{
const struct brw_vue_prog_data *prog_data =
(const struct brw_vue_prog_data *)bin->prog_data;
return (prog_data->vue_map.num_slots + 1) / 2 - get_urb_output_offset();
}
static void
emit_3dstate_vs(struct anv_pipeline *pipeline)
{
const struct gen_device_info *devinfo = &pipeline->device->info;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_shader_bin *vs_bin =
pipeline->shaders[MESA_SHADER_VERTEX];
assert(anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX));
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
vs.FunctionEnable = true;
vs.StatisticsEnable = true;
vs.KernelStartPointer = vs_bin->kernel.offset;
#if GEN_GEN >= 8
vs.SIMD8DispatchEnable =
vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
#endif
assert(!vs_prog_data->base.base.use_alt_mode);
vs.SingleVertexDispatch = false;
vs.VectorMaskEnable = false;
vs.SamplerCount = get_sampler_count(vs_bin);
vs.BindingTableEntryCount = get_binding_table_entry_count(vs_bin);
vs.FloatingPointMode = IEEE754;
vs.IllegalOpcodeExceptionEnable = false;
vs.SoftwareExceptionEnable = false;
vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
vs.VertexCacheDisable = false;
vs.VertexURBEntryReadLength = vs_prog_data->base.urb_read_length;
vs.VertexURBEntryReadOffset = 0;
vs.DispatchGRFStartRegisterForURBData =
vs_prog_data->base.base.dispatch_grf_start_reg;
#if GEN_GEN >= 8
vs.VertexURBEntryOutputReadOffset = get_urb_output_offset();
vs.VertexURBEntryOutputLength = get_urb_output_length(vs_bin);
/* TODO */
vs.UserClipDistanceClipTestEnableBitmask = 0;
vs.UserClipDistanceCullTestEnableBitmask = 0;
#endif
vs.PerThreadScratchSpace = get_scratch_space(vs_bin);
vs.ScratchSpaceBasePointer =
get_scratch_address(pipeline, MESA_SHADER_VERTEX, vs_bin);
}
}
#endif /* GENX_PIPELINE_UTIL_H */ #endif /* GENX_PIPELINE_UTIL_H */