aco: set vm for pos0 exports on GFX10
RADV's LLVM backend and radeonsi does the same thing. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Cc: 19.3 <mesa-stable@lists.freedesktop.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3081>
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@@ -627,7 +627,7 @@ void fix_exports(asm_context& ctx, std::vector<uint32_t>& out, Program* program)
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exp->enabled_mask = 0;
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exp->compressed = false;
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exp->done = true;
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exp->valid_mask = program->stage & hw_fs;
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exp->valid_mask = (program->stage & hw_fs) || program->chip_class >= GFX10;
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if (program->stage & hw_fs)
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exp->dest = 9; /* NULL */
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else
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@@ -7739,7 +7739,10 @@ static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *nex
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else
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exp->operands[i] = Operand(v1);
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}
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exp->valid_mask = false;
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/* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
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* Setting valid_mask=1 prevents it and has no other effect.
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*/
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exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
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exp->done = false;
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exp->compressed = false;
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if (is_pos)
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@@ -7779,7 +7782,7 @@ static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
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exp->enabled_mask |= 0x4;
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}
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}
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exp->valid_mask = false;
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exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
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exp->done = false;
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exp->compressed = false;
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exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
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