intel/ir: Pass block cycle count information explicitly to disassembler.

So we can eventually remove the cycle count estimates from the CFG
data structure and consolidate performance information in the
brw::performance object.

It would be cleaner to pass the brw::performance object directly to
the disassembler but that isn't straightforward since the disassembler
is built as a plain C file unlike the rest of the compiler back-end.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

src/intel/compiler/brw_disasm_info.c

@@ -31,7 +31,8 @@ __attribute__((weak)) void nir_print_instr(UNUSED const nir_instr *instr,
                                            UNUSED FILE *fp) {}
 
 void
-dump_assembly(void *assembly, struct disasm_info *disasm)
+dump_assembly(void *assembly, struct disasm_info *disasm,
+              const unsigned *block_latency)
 {
    const struct gen_device_info *devinfo = disasm->devinfo;
    const char *last_annotation_string = NULL;
@@ -55,7 +56,10 @@ dump_assembly(void *assembly, struct disasm_info *disasm)
             struct bblock_t *predecessor_block = predecessor_link->block;
             fprintf(stderr, " <-B%d", predecessor_block->num);
          }
-         fprintf(stderr, " (%u cycles)\n", group->block_start->cycle_count);
+         if (block_latency)
+            fprintf(stderr, " (%u cycles)",
+                    block_latency[group->block_start->num]);
+         fprintf(stderr, "\n");
       }
 
       if (last_annotation_ir != group->ir) {

src/intel/compiler/brw_disasm_info.h

@@ -65,7 +65,8 @@ struct disasm_info {
 };
 
 void
-dump_assembly(void *assembly, struct disasm_info *disasm);
+dump_assembly(void *assembly, struct disasm_info *disasm,
+              const unsigned *block_latency);
 
 struct disasm_info *
 disasm_initialize(const struct gen_device_info *devinfo,

src/intel/compiler/brw_fs_generator.cpp

@@ -2472,7 +2472,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
 
       /* overriding the shader makes disasm_info invalid */
       if (!brw_try_override_assembly(p, start_offset, sha1buf)) {
-         dump_assembly(p->store, disasm_info);
+         dump_assembly(p->store, disasm_info, perf.block_latency);
       } else {
          fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
       }

src/intel/compiler/brw_vec4_generator.cpp

@@ -2227,7 +2227,7 @@ generate_code(struct brw_codegen *p,
 
       /* overriding the shader makes disasm_info invalid */
       if (!brw_try_override_assembly(p, 0, sha1buf)) {
-         dump_assembly(p->store, disasm_info);
+         dump_assembly(p->store, disasm_info, perf.block_latency);
       } else {
          fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
       }

src/intel/compiler/test_eu_validate.cpp

@@ -110,7 +110,7 @@ validate(struct brw_codegen *p)
                                         p->next_insn_offset, disasm);
 
    if (print) {
-      dump_assembly(p->store, disasm);
+      dump_assembly(p->store, disasm, NULL);
    }
    ralloc_free(disasm);