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radv/nir: lower esgs_vertex_stride for GS compiled separately on GFX9+

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The ESGS vertex stride would be emitted at draw time using the number
of VS/TES outputs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27388>
This commit is contained in:
Samuel Pitoiset
2024-01-30 11:11:37 +01:00
committed by Marge Bot
parent d777cbf66c
commit 482dbacdeb
1 changed files with 7 additions and 3 deletions
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10
src/amd/vulkan/nir/radv_nir_lower_abi.c
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@@ -285,9 +285,13 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
case nir_intrinsic_load_esgs_vertex_stride_amd: {
/* Emulate VGT_ESGS_RING_ITEMSIZE on GFX9+ to reduce context register writes. */
assert(s->gfx_level >= GFX9);
const unsigned stride =
s->info->is_ngg ? s->info->ngg_info.vgt_esgs_ring_itemsize : s->info->gs_ring_info.vgt_esgs_ring_itemsize;
replacement = nir_imm_int(b, stride);
if (s->info->merged_shader_compiled_separately) {
replacement = ac_nir_load_arg(b, &s->args->ac, s->args->vgt_esgs_ring_itemsize);
} else {
const unsigned stride =
s->info->is_ngg ? s->info->ngg_info.vgt_esgs_ring_itemsize : s->info->gs_ring_info.vgt_esgs_ring_itemsize;
replacement = nir_imm_int(b, stride);
}
break;
}
case nir_intrinsic_load_hs_out_patch_data_offset_amd: {