intel,crocus,iris: Use align64 instead of ALIGN for 64 bit value parameter

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26864>
This commit is contained in:
Yonggang Luo
2023-06-29 11:34:46 +08:00
committed by Marge Bot
parent 5a2aa3ff88
commit 472b6f5379
5 changed files with 10 additions and 10 deletions

View File

@@ -404,7 +404,7 @@ bo_alloc_internal(struct crocus_bufmgr *bufmgr,
* at this size, a multiple of the page size.
*/
uint64_t bo_size =
bucket ? bucket->size : MAX2(ALIGN(size, page_size), page_size);
bucket ? bucket->size : MAX2(align64(size, page_size), page_size);
simple_mtx_lock(&bufmgr->lock);

View File

@@ -502,7 +502,7 @@ crocus_resource_configure_aux(struct crocus_screen *screen,
return false;
/* Increase the aux offset if the main and aux surfaces will share a BO. */
res->aux.offset = ALIGN(res->surf.size_B, res->aux.surf.alignment_B);
res->aux.offset = (uint32_t)align64(res->surf.size_B, res->aux.surf.alignment_B);
uint64_t size = res->aux.surf.size_B;
/* Allocate space in the buffer for storing the clear color. On modern
@@ -515,7 +515,7 @@ crocus_resource_configure_aux(struct crocus_screen *screen,
* starts at a 4K alignment. We believe that 256B might be enough, but due
* to lack of testing we will leave this as 4K for now.
*/
size = ALIGN(size, 4096);
size = align64(size, 4096);
*aux_size_B = size;
if (isl_aux_usage_has_hiz(res->aux.usage)) {

View File

@@ -1088,7 +1088,7 @@ alloc_fresh_bo(struct iris_bufmgr *bufmgr, uint64_t bo_size, unsigned flags)
* be defensive in case any of those bypass the caches and end up here.
*/
if (bo_size >= 1024 * 1024)
bo_size = ALIGN(bo_size, 2 * 1024 * 1024);
bo_size = align64(bo_size, 2 * 1024 * 1024);
bo->real.heap = flags_to_heap(bufmgr, flags);
@@ -1185,7 +1185,7 @@ iris_bo_alloc(struct iris_bufmgr *bufmgr,
* at this size, a multiple of the page size.
*/
uint64_t bo_size =
bucket ? bucket->size : MAX2(ALIGN(size, page_size), page_size);
bucket ? bucket->size : MAX2(align64(size, page_size), page_size);
enum iris_mmap_mode mmap_mode = heap_to_mmap_mode(bufmgr, heap);
simple_mtx_lock(&bufmgr->lock);

View File

@@ -1156,14 +1156,14 @@ iris_resource_create_for_image(struct pipe_screen *pscreen,
/* Allocate space for the aux buffer. */
if (res->aux.surf.size_B > 0) {
res->aux.offset = ALIGN(bo_size, res->aux.surf.alignment_B);
res->aux.offset = (uint32_t)align64(bo_size, res->aux.surf.alignment_B);
bo_size = res->aux.offset + res->aux.surf.size_B;
}
/* Allocate space for the extra aux buffer. */
if (res->aux.extra_aux.surf.size_B > 0) {
res->aux.extra_aux.offset =
ALIGN(bo_size, res->aux.extra_aux.surf.alignment_B);
(uint32_t)align64(bo_size, res->aux.extra_aux.surf.alignment_B);
bo_size = res->aux.extra_aux.offset + res->aux.extra_aux.surf.size_B;
}
@@ -1174,7 +1174,7 @@ iris_resource_create_for_image(struct pipe_screen *pscreen,
* to lack of testing we will leave this as 4K for now.
*/
if (iris_get_aux_clear_color_state_size(screen, res) > 0) {
res->aux.clear_color_offset = ALIGN(bo_size, 4096);
res->aux.clear_color_offset = align64(bo_size, 4096);
bo_size = res->aux.clear_color_offset +
iris_get_aux_clear_color_state_size(screen, res);
}
@@ -1517,7 +1517,7 @@ iris_resource_from_memobj_wrapper(struct pipe_screen *pscreen,
/* Stencil offset in the buffer without aux. */
uint64_t s_offset = offset +
ALIGN(res->surf.size_B, res->surf.alignment_B);
align64(res->surf.size_B, res->surf.alignment_B);
prsc->format = format; /* frob the format back to the "external" format */

View File

@@ -384,7 +384,7 @@ anv_h265_decode_video(struct anv_cmd_buffer *cmd_buffer,
};
indirect.HCPIndirectBitstreamObjectAccessUpperBound =
anv_address_add(src_buffer->address, ALIGN(frame_info->srcBufferRange, 4096));
anv_address_add(src_buffer->address, align64(frame_info->srcBufferRange, 4096));
indirect.HCPIndirectCUObjectMemoryAddressAttributes = (struct GENX(MEMORYADDRESSATTRIBUTES)) {
.MOCS = anv_mocs(cmd_buffer->device, NULL, 0),