i965/fs: Print the scheduler mode.
Line wrap some awfully long lines while we are here. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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committed by
Ian Romanick

parent
dabb5d4bee
commit
46a3ea06be
@@ -7213,6 +7213,12 @@ fs_visitor::allocate_registers(unsigned min_dispatch_width, bool allow_spilling)
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SCHEDULE_PRE_LIFO,
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};
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static const char *scheduler_mode_name[] = {
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"top-down",
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"non-lifo",
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"lifo"
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};
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bool spill_all = allow_spilling && (INTEL_DEBUG & DEBUG_SPILL_FS);
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/* Try each scheduling heuristic to see if it can successfully register
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@@ -7221,6 +7227,7 @@ fs_visitor::allocate_registers(unsigned min_dispatch_width, bool allow_spilling)
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*/
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for (unsigned i = 0; i < ARRAY_SIZE(pre_modes); i++) {
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schedule_instructions(pre_modes[i]);
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this->shader_stats.scheduler_mode = scheduler_mode_name[i];
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if (0) {
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assign_regs_trivial();
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@@ -53,6 +53,7 @@ offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta)
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#define UBO_START ((1 << 16) - 4)
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struct shader_stats {
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const char *scheduler_mode;
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unsigned promoted_constants;
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};
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@@ -2250,10 +2250,17 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
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if (unlikely(debug_flag)) {
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fprintf(stderr, "Native code for %s\n"
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"SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
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" bytes (%.0f%%)\n",
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shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
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spill_count, fill_count, shader_stats.promoted_constants, before_size, after_size,
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"SIMD%d shader: %d instructions. %d loops. %u cycles. "
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"%d:%d spills:fills. "
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"scheduled with mode %s. "
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"Promoted %u constants. "
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"Compacted %d to %d bytes (%.0f%%)\n",
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shader_name, dispatch_width, before_size / 16,
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loop_count, cfg->cycle_count,
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spill_count, fill_count,
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shader_stats.scheduler_mode,
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shader_stats.promoted_constants,
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before_size, after_size,
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100.0f * (before_size - after_size) / before_size);
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dump_assembly(p->store, disasm_info);
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@@ -2263,13 +2270,17 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
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compiler->shader_debug_log(log_data,
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"%s SIMD%d shader: %d inst, %d loops, %u cycles, "
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"%d:%d spills:fills, Promoted %u constants, "
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"%d:%d spills:fills, "
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"scheduled with mode %s, "
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"Promoted %u constants, "
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"compacted %d to %d bytes.",
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_mesa_shader_stage_to_abbrev(stage),
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dispatch_width, before_size / 16,
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loop_count, cfg->cycle_count, spill_count,
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fill_count, shader_stats.promoted_constants, before_size,
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after_size);
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loop_count, cfg->cycle_count,
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spill_count, fill_count,
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shader_stats.scheduler_mode,
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shader_stats.promoted_constants,
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before_size, after_size);
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return start_offset;
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}
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@@ -952,6 +952,7 @@ fs_visitor::init()
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this->pull_constant_loc = NULL;
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this->push_constant_loc = NULL;
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this->shader_stats.scheduler_mode = NULL;
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this->shader_stats.promoted_constants = 0,
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this->grf_used = 0;
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