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intel/fs: Fix PS thread payload setup for depth_w_coef_reg.

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It's not replicated per SIMD16 half of a SIMD32 thread on the PS
payload.  Make fs_visitor::payload::depth_w_coef_reg a scalar rather
than an array.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26585>
This commit is contained in:
Francisco Jerez
2022-06-11 17:35:00 -07:00
committed by Marge Bot
parent 09ea840987
commit 4672fcbc76
3 changed files with 8 additions and 7 deletions
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2
src/intel/compiler/brw_fs.h
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@@ -137,7 +137,7 @@ struct fs_thread_payload : public thread_payload {
uint8_t dest_depth_reg[2];
uint8_t sample_pos_reg[2];
uint8_t sample_mask_in_reg[2];
uint8_t depth_w_coef_reg[2];
uint8_t depth_w_coef_reg;
uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2];
};

11
src/intel/compiler/brw_fs_thread_payload.cpp
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@@ -210,12 +210,13 @@ setup_fs_payload_gfx6(fs_thread_payload &payload,
payload.sample_mask_in_reg[j] = payload.num_regs;
payload.num_regs += payload_width / 8;
}
}
/* R66: Source Depth and/or W Attribute Vertex Deltas */
if (prog_data->uses_depth_w_coefficients) {
payload.depth_w_coef_reg[j] = payload.num_regs;
payload.num_regs++;
}
/* R66: Source Depth and/or W Attribute Vertex Deltas */
if (prog_data->uses_depth_w_coefficients) {
assert(v.max_polygons == 1);
payload.depth_w_coef_reg = payload.num_regs;
payload.num_regs++;
}
if (v.nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {

2
src/intel/compiler/brw_fs_visitor.cpp
View File

@@ -435,7 +435,7 @@ fs_visitor::emit_interpolation_setup_gfx6()
* pixels locations, here we recompute the Z value with 2 coefficients
* in X & Y axis.
*/
fs_reg coef_payload = fetch_payload_reg(abld, fs_payload().depth_w_coef_reg, BRW_REGISTER_TYPE_F);
fs_reg coef_payload = brw_vec8_grf(fs_payload().depth_w_coef_reg, 0);
const fs_reg x_start = brw_vec1_grf(coef_payload.nr, 2);
const fs_reg y_start = brw_vec1_grf(coef_payload.nr, 6);
const fs_reg z_cx = brw_vec1_grf(coef_payload.nr, 1);