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r600/sfn: simplify IO lowering and fix TESS IO lowering

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Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7715>
This commit is contained in:
Gert Wollny
2020-11-25 20:44:13 +01:00
committed by Marge Bot
parent efcb7b7050
commit 45f17702db
2 changed files with 47 additions and 69 deletions
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52
src/gallium/drivers/r600/sfn/sfn_nir.cpp
View File

@@ -825,51 +825,35 @@ int r600_shader_from_nir(struct r600_context *rctx,
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, r600_glsl_type_size, NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32); nir_lower_io_lower_64bit_to_32);
if (sel->nir->info.stage == MESA_SHADER_VERTEX) { nir_variable_mode io_modes = (nir_variable_mode)0;
NIR_PASS_V(sel->nir, r600_vectorize_vs_inputs); if (sel->nir->info.stage != MESA_SHADER_VERTEX)
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size, io_modes = nir_var_shader_in;
if (sel->nir->info.stage != MESA_SHADER_FRAGMENT)
io_modes |= nir_var_shader_out;
NIR_PASS_V(sel->nir, nir_lower_io, io_modes, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32); nir_lower_io_lower_64bit_to_32);
if (key->vs.as_ls)
NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode); NIR_PASS_V(sel->nir, nir_opt_constant_folding);
} NIR_PASS_V(sel->nir, nir_io_add_const_offset_to_base, io_modes);
if (sel->nir->info.stage == MESA_SHADER_VERTEX)
NIR_PASS_V(sel->nir, r600_vectorize_vs_inputs);
if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) { if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size,
(nir_lower_io_options)
(nir_lower_io_lower_64bit_to_32));
NIR_PASS_V(sel->nir, r600_lower_fs_pos_input); NIR_PASS_V(sel->nir, r600_lower_fs_pos_input);
NIR_PASS_V(sel->nir, r600_lower_fs_out_to_vector); NIR_PASS_V(sel->nir, r600_lower_fs_out_to_vector);
} }
if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL) {
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode);
}
if (sel->nir->info.stage == MESA_SHADER_GEOMETRY) {
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
}
if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL || if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL ||
sel->nir->info.stage == MESA_SHADER_TESS_EVAL) { sel->nir->info.stage == MESA_SHADER_TESS_EVAL ||
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size, (sel->nir->info.stage == MESA_SHADER_VERTEX && key->vs.as_ls)) {
nir_lower_io_lower_64bit_to_32); auto prim_type = sel->nir->info.stage == MESA_SHADER_TESS_EVAL ?
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size, sel->nir->info.tess.primitive_mode: key->tcs.prim_mode;
nir_lower_io_lower_64bit_to_32);
}
if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL ||
sel->nir->info.stage == MESA_SHADER_TESS_EVAL) {
auto prim_type = sel->nir->info.stage == MESA_SHADER_TESS_CTRL ?
key->tcs.prim_mode : sel->nir->info.tess.primitive_mode;
NIR_PASS_V(sel->nir, r600_lower_tess_io, static_cast<pipe_prim_type>(prim_type)); NIR_PASS_V(sel->nir, r600_lower_tess_io, static_cast<pipe_prim_type>(prim_type));
} }
if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL) if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL)
NIR_PASS_V(sel->nir, r600_append_tcs_TF_emission, NIR_PASS_V(sel->nir, r600_append_tcs_TF_emission,
(pipe_prim_type)key->tcs.prim_mode); (pipe_prim_type)key->tcs.prim_mode);

38
src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp
View File

@@ -34,12 +34,11 @@ emit_load_param_base(nir_builder *b, nir_intrinsic_op op)
return &result->dest.ssa; return &result->dest.ssa;
} }
static int get_tcs_varying_offset(nir_shader *nir, nir_variable_mode mode, static int get_tcs_varying_offset(nir_intrinsic_instr *op)
unsigned index)
{ {
nir_foreach_variable_with_modes(var, nir, mode) { unsigned location = nir_intrinsic_io_semantics(op).location;
if (var->data.driver_location == index) {
switch (var->data.location) { switch (location) {
case VARYING_SLOT_POS: case VARYING_SLOT_POS:
return 0; return 0;
case VARYING_SLOT_PSIZ: case VARYING_SLOT_PSIZ:
@@ -53,15 +52,12 @@ static int get_tcs_varying_offset(nir_shader *nir, nir_variable_mode mode,
case VARYING_SLOT_TESS_LEVEL_INNER: case VARYING_SLOT_TESS_LEVEL_INNER:
return 0x10; return 0x10;
default: default:
if (var->data.location >= VARYING_SLOT_VAR0 && if (location >= VARYING_SLOT_VAR0 &&
var->data.location <= VARYING_SLOT_VAR31) location <= VARYING_SLOT_VAR31)
return 0x10 * (var->data.location - VARYING_SLOT_VAR0) + 0x40; return 0x10 * (location - VARYING_SLOT_VAR0) + 0x40;
if (var->data.location >= VARYING_SLOT_PATCH0) { if (location >= VARYING_SLOT_PATCH0) {
return 0x10 * (var->data.location - VARYING_SLOT_PATCH0) + 0x20; return 0x10 * (location - VARYING_SLOT_PATCH0) + 0x20;
}
}
/* TODO: PATCH is missing */
} }
} }
return 0; return 0;
@@ -94,7 +90,7 @@ emil_lsd_in_addr(nir_builder *b, nir_ssa_def *base, nir_ssa_def *patch_id, nir_i
addr = r600_umad_24(b, nir_channel(b, base, 1), addr = r600_umad_24(b, nir_channel(b, base, 1),
op->src[0].ssa, addr); op->src[0].ssa, addr);
auto offset = nir_imm_int(b, get_tcs_varying_offset(b->shader, nir_var_shader_in, nir_intrinsic_base(op))); auto offset = nir_imm_int(b, get_tcs_varying_offset(op));
auto idx2 = nir_src_as_const_value(op->src[1]); auto idx2 = nir_src_as_const_value(op->src[1]);
if (!idx2 || idx2->u32 != 0) if (!idx2 || idx2->u32 != 0)
@@ -112,8 +108,7 @@ emil_lsd_out_addr(nir_builder *b, nir_ssa_def *base, nir_ssa_def *patch_id, nir_
nir_channel(b, base, 2)); nir_channel(b, base, 2));
nir_ssa_def *addr2 = r600_umad_24(b, nir_channel(b, base, 1), nir_ssa_def *addr2 = r600_umad_24(b, nir_channel(b, base, 1),
op->src[src_offset].ssa, addr1); op->src[src_offset].ssa, addr1);
int offset = get_tcs_varying_offset(op);
int offset = get_tcs_varying_offset(b->shader, mode, nir_intrinsic_base(op));
return nir_iadd(b, nir_iadd(b, addr2, return nir_iadd(b, nir_iadd(b, addr2,
nir_ishl(b, op->src[src_offset + 1].ssa, nir_imm_int(b,4))), nir_ishl(b, op->src[src_offset + 1].ssa, nir_imm_int(b,4))),
nir_imm_int(b, offset)); nir_imm_int(b, offset));
@@ -185,10 +180,9 @@ emit_store_lds(nir_builder *b, nir_intrinsic_instr *op, nir_ssa_def *addr)
} }
static nir_ssa_def * static nir_ssa_def *
emil_tcs_io_offset(nir_builder *b, nir_ssa_def *addr, nir_intrinsic_instr *op, nir_variable_mode mode, int src_offset) emil_tcs_io_offset(nir_builder *b, nir_ssa_def *addr, nir_intrinsic_instr *op, int src_offset)
{ {
int offset = get_tcs_varying_offset(op);
int offset = get_tcs_varying_offset(b->shader, mode, nir_intrinsic_base(op));
return nir_iadd(b, nir_iadd(b, addr, return nir_iadd(b, nir_iadd(b, addr,
nir_ishl(b, op->src[src_offset].ssa, nir_imm_int(b,4))), nir_ishl(b, op->src[src_offset].ssa, nir_imm_int(b,4))),
nir_imm_int(b, offset)); nir_imm_int(b, offset));
@@ -264,20 +258,20 @@ r600_lower_tess_io_impl(nir_builder *b, nir_instr *instr, enum pipe_prim_type pr
nir_build_alu(b, nir_op_umul24, nir_build_alu(b, nir_op_umul24,
nir_channel(b, load_out_param_base, 1), nir_channel(b, load_out_param_base, 1),
rel_patch_id, NULL, NULL); rel_patch_id, NULL, NULL);
addr = emil_tcs_io_offset(b, addr, op, nir_var_shader_out, 1); addr = emil_tcs_io_offset(b, addr, op, 1);
emit_store_lds(b, op, addr); emit_store_lds(b, op, addr);
nir_instr_remove(instr); nir_instr_remove(instr);
return true; return true;
} }
case nir_intrinsic_load_output: { case nir_intrinsic_load_output: {
nir_ssa_def *addr = r600_tcs_base_address(b, load_out_param_base, rel_patch_id); nir_ssa_def *addr = r600_tcs_base_address(b, load_out_param_base, rel_patch_id);
addr = emil_tcs_io_offset(b, addr, op, nir_var_shader_out, 0); addr = emil_tcs_io_offset(b, addr, op, 0);
replace_load_instr(b, op, addr); replace_load_instr(b, op, addr);
return true; return true;
} }
case nir_intrinsic_load_input: { case nir_intrinsic_load_input: {
nir_ssa_def *addr = r600_tcs_base_address(b, load_in_param_base, rel_patch_id); nir_ssa_def *addr = r600_tcs_base_address(b, load_in_param_base, rel_patch_id);
addr = emil_tcs_io_offset(b, addr, op, nir_var_shader_in, 0); addr = emil_tcs_io_offset(b, addr, op, 0);
replace_load_instr(b, op, addr); replace_load_instr(b, op, addr);
return true; return true;
} }