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r600/sfn: simplify IO lowering and fix TESS IO lowering

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Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7715>
This commit is contained in:
Gert Wollny
2020-11-25 20:44:13 +01:00
committed by Marge Bot
parent efcb7b7050
commit 45f17702db
2 changed files with 47 additions and 69 deletions
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52
src/gallium/drivers/r600/sfn/sfn_nir.cpp
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@@ -825,51 +825,35 @@ int r600_shader_from_nir(struct r600_context *rctx,
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
if (sel->nir->info.stage == MESA_SHADER_VERTEX) {
nir_variable_mode io_modes = (nir_variable_mode)0;
if (sel->nir->info.stage != MESA_SHADER_VERTEX)
io_modes = nir_var_shader_in;
if (sel->nir->info.stage != MESA_SHADER_FRAGMENT)
io_modes |= nir_var_shader_out;
NIR_PASS_V(sel->nir, nir_lower_io, io_modes, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
NIR_PASS_V(sel->nir, nir_opt_constant_folding);
NIR_PASS_V(sel->nir, nir_io_add_const_offset_to_base, io_modes);
if (sel->nir->info.stage == MESA_SHADER_VERTEX)
NIR_PASS_V(sel->nir, r600_vectorize_vs_inputs);
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
if (key->vs.as_ls)
NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode);
}
if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size,
(nir_lower_io_options)
(nir_lower_io_lower_64bit_to_32));
NIR_PASS_V(sel->nir, r600_lower_fs_pos_input);
NIR_PASS_V(sel->nir, r600_lower_fs_out_to_vector);
}
if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL) {
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
NIR_PASS_V(sel->nir, r600_lower_tess_io, (pipe_prim_type)key->tcs.prim_mode);
}
if (sel->nir->info.stage == MESA_SHADER_GEOMETRY) {
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
}
if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL ||
sel->nir->info.stage == MESA_SHADER_TESS_EVAL) {
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_out, r600_glsl_type_size,
nir_lower_io_lower_64bit_to_32);
}
if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL ||
sel->nir->info.stage == MESA_SHADER_TESS_EVAL) {
auto prim_type = sel->nir->info.stage == MESA_SHADER_TESS_CTRL ?
key->tcs.prim_mode : sel->nir->info.tess.primitive_mode;
sel->nir->info.stage == MESA_SHADER_TESS_EVAL ||
(sel->nir->info.stage == MESA_SHADER_VERTEX && key->vs.as_ls)) {
auto prim_type = sel->nir->info.stage == MESA_SHADER_TESS_EVAL ?
sel->nir->info.tess.primitive_mode: key->tcs.prim_mode;
NIR_PASS_V(sel->nir, r600_lower_tess_io, static_cast<pipe_prim_type>(prim_type));
}
if (sel->nir->info.stage == MESA_SHADER_TESS_CTRL)
NIR_PASS_V(sel->nir, r600_append_tcs_TF_emission,
(pipe_prim_type)key->tcs.prim_mode);