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intel/fs: Use write masks from store_reg intrinsics

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Fixes: b8209d69ff ("intel/fs: Add support for new-style registers")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24310>
This commit is contained in:
Faith Ekstrand
2023-07-24 17:06:32 -05:00
committed by Marge Bot
parent d89ca14e71
commit 45ee952efb
2 changed files with 25 additions and 7 deletions
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1
src/intel/compiler/brw_fs.h
View File

@@ -386,6 +386,7 @@ public:
fs_reg get_nir_src(const nir_src &src); fs_reg get_nir_src(const nir_src &src);
fs_reg get_nir_src_imm(const nir_src &src); fs_reg get_nir_src_imm(const nir_src &src);
fs_reg get_nir_dest(const nir_dest &dest); fs_reg get_nir_dest(const nir_dest &dest);
nir_component_mask_t get_nir_write_mask(const nir_alu_dest &dest);
fs_reg get_resource_nir_src(const nir_src &src); fs_reg get_resource_nir_src(const nir_src &src);
fs_reg try_rebuild_resource(const brw::fs_builder &bld, fs_reg try_rebuild_resource(const brw::fs_builder &bld,
nir_ssa_def *resource_def); nir_ssa_def *resource_def);

31
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -688,8 +688,9 @@ fs_visitor::prepare_alu_destination_and_sources(const fs_builder &bld,
/* Since NIR is doing the scalarizing for us, we should only ever see /* Since NIR is doing the scalarizing for us, we should only ever see
* vectorized operations with a single channel. * vectorized operations with a single channel.
*/ */
assert(util_bitcount(instr->dest.write_mask) == 1); nir_component_mask_t write_mask = get_nir_write_mask(instr->dest);
channel = ffs(instr->dest.write_mask) - 1; assert(util_bitcount(write_mask) == 1);
channel = ffs(write_mask) - 1;
result = offset(result, bld, channel); result = offset(result, bld, channel);
} }
@@ -799,8 +800,9 @@ fs_visitor::emit_fsign(const fs_builder &bld, const nir_alu_instr *instr,
/* Since NIR is doing the scalarizing for us, we should only ever see /* Since NIR is doing the scalarizing for us, we should only ever see
* vectorized operations with a single channel. * vectorized operations with a single channel.
*/ */
assert(util_bitcount(instr->dest.write_mask) == 1); nir_component_mask_t write_mask = get_nir_write_mask(instr->dest);
channel = ffs(instr->dest.write_mask) - 1; assert(util_bitcount(write_mask) == 1);
channel = ffs(write_mask) - 1;
} }
op[0] = offset(op[0], bld, fsign_instr->src[0].swizzle[channel]); op[0] = offset(op[0], bld, fsign_instr->src[0].swizzle[channel]);
@@ -992,10 +994,11 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
} }
} }
unsigned last_bit = util_last_bit(instr->dest.write_mask); nir_component_mask_t write_mask = get_nir_write_mask(instr->dest);
unsigned last_bit = util_last_bit(write_mask);
for (unsigned i = 0; i < last_bit; i++) { for (unsigned i = 0; i < last_bit; i++) {
if (!(instr->dest.write_mask & (1 << i))) if (!(write_mask & (1 << i)))
continue; continue;
if (instr->op == nir_op_mov) { if (instr->op == nir_op_mov) {
@@ -1013,7 +1016,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
*/ */
if (need_extra_copy) { if (need_extra_copy) {
for (unsigned i = 0; i < last_bit; i++) { for (unsigned i = 0; i < last_bit; i++) {
if (!(instr->dest.write_mask & (1 << i))) if (!(write_mask & (1 << i)))
continue; continue;
bld.MOV(offset(result, bld, i), offset(temp, bld, i)); bld.MOV(offset(result, bld, i), offset(temp, bld, i));
@@ -2078,6 +2081,20 @@ fs_visitor::get_nir_dest(const nir_dest &dest)
} }
} }
nir_component_mask_t
fs_visitor::get_nir_write_mask(const nir_alu_dest &dest)
{
assert(dest.dest.is_ssa);
assert(dest.write_mask == nir_component_mask(dest.dest.ssa.num_components));
nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&dest.dest.ssa);
if (!store_reg) {
return nir_component_mask(dest.dest.ssa.num_components);
} else {
return nir_intrinsic_write_mask(store_reg);
}
}
static fs_inst * static fs_inst *
emit_pixel_interpolater_send(const fs_builder &bld, emit_pixel_interpolater_send(const fs_builder &bld,
enum opcode opcode, enum opcode opcode,