From 44feff93c2d67e52699ace7002f3a2319d5ef6d5 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Mon, 7 Mar 2022 16:27:02 +0100 Subject: [PATCH] broadcom/compiler: don't always assign r5 if available MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead, only favor assigning r5 if we have first decided to assign an accumulator. This helps with assining r5 to short lived uniforms, favoring accumulator rotation to facilitate QPU merges. total instructions in shared programs: 12656164 -> 12628339 (-0.22%) instructions in affected programs: 5368373 -> 5340548 (-0.52%) helped: 17420 HURT: 9996 total uniforms in shared programs: 3704776 -> 3704863 (<.01%) uniforms in affected programs: 12247 -> 12334 (0.71%) helped: 23 HURT: 78 total max-temps in shared programs: 2153505 -> 2152684 (-0.04%) max-temps in affected programs: 26468 -> 25647 (-3.10%) helped: 569 HURT: 328 total fills in shared programs: 4656 -> 4657 (0.02%) fills in affected programs: 43 -> 44 (2.33%) helped: 0 HURT: 1 total sfu-stalls in shared programs: 34728 -> 34403 (-0.94%) sfu-stalls in affected programs: 3411 -> 3086 (-9.53%) helped: 842 HURT: 534 Reviewed-by: Alejandro Piñeiro Part-of: --- src/broadcom/compiler/vir_register_allocate.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/broadcom/compiler/vir_register_allocate.c b/src/broadcom/compiler/vir_register_allocate.c index 46c7e52eed6..96f8d1cc233 100644 --- a/src/broadcom/compiler/vir_register_allocate.c +++ b/src/broadcom/compiler/vir_register_allocate.c @@ -703,6 +703,16 @@ v3d_ra_select_accum(struct v3d_ra_select_callback_data *v3d_ra, BITSET_WORD *regs, unsigned int *out) { + /* Choose r5 for our ldunifs if possible (nobody else can load to that + * reg, and it keeps the QPU cond field free from being occupied by + * ldunifrf). + */ + int r5 = ACC_INDEX + 5; + if (BITSET_TEST(regs, r5)) { + *out = r5; + return true; + } + /* Round-robin through our accumulators to give post-RA instruction * selection more options. */ @@ -743,14 +753,6 @@ static unsigned int v3d_ra_select_callback(unsigned int n, BITSET_WORD *regs, void *data) { struct v3d_ra_select_callback_data *v3d_ra = data; - int r5 = ACC_INDEX + 5; - - /* Choose r5 for our ldunifs if possible (nobody else can load to that - * reg, and it keeps the QPU cond field free from being occupied by - * ldunifrf). - */ - if (BITSET_TEST(regs, r5)) - return r5; unsigned int reg; if (v3d_ra_favor_accum(v3d_ra, regs, v3d_ra->nodes->info[n].priority) &&