diff --git a/src/imagination/rogue/rogue.c b/src/imagination/rogue/rogue.c index 94f8d5f3f7d..d8f23bc5f49 100644 --- a/src/imagination/rogue/rogue.c +++ b/src/imagination/rogue/rogue.c @@ -1209,7 +1209,9 @@ rogue_compiler *rogue_compiler_create(const struct pvr_device_info *dev_info) * \return A pointer to the new build context, or NULL on failure. */ PUBLIC -rogue_build_ctx *rogue_build_context_create(rogue_compiler *compiler) +rogue_build_ctx * +rogue_build_context_create(rogue_compiler *compiler, + struct pvr_pipeline_layout *pipeline_layout) { rogue_build_ctx *ctx; @@ -1218,6 +1220,7 @@ rogue_build_ctx *rogue_build_context_create(rogue_compiler *compiler) return NULL; ctx->compiler = compiler; + ctx->pipeline_layout = pipeline_layout; /* nir/rogue/binary shaders need to be default-zeroed; * this is taken care of by rzalloc_size. diff --git a/src/imagination/rogue/rogue.h b/src/imagination/rogue/rogue.h index dcd78a5da2c..4afc6e91927 100644 --- a/src/imagination/rogue/rogue.h +++ b/src/imagination/rogue/rogue.h @@ -2773,10 +2773,13 @@ typedef struct rogue_build_ctx { rogue_common_build_data common_data[MESA_SHADER_FRAGMENT + 1]; rogue_build_data stage_data; + struct pvr_pipeline_layout *pipeline_layout; unsigned next_ssa_idx; } rogue_build_ctx; -rogue_build_ctx *rogue_build_context_create(rogue_compiler *compiler); +rogue_build_ctx * +rogue_build_context_create(rogue_compiler *compiler, + struct pvr_pipeline_layout *pipeline_layout); void rogue_collect_io_data(rogue_build_ctx *ctx, nir_shader *nir); diff --git a/src/imagination/rogue/rogue_build_data.c b/src/imagination/rogue/rogue_build_data.c index dd6b68cac27..6cb63787ddc 100644 --- a/src/imagination/rogue/rogue_build_data.c +++ b/src/imagination/rogue/rogue_build_data.c @@ -362,109 +362,6 @@ static void collect_io_data_vs(struct rogue_common_build_data *common_data, vs_data->num_varyings = count_vs_varyings(&vs_data->outputs); } -/** - * \brief Allocates the shared registers that will contain the UBOs. - * - * \param[in] ubo_data The UBO data. - * \return The total number of coefficient registers required by the iterators. - */ -static unsigned alloc_ubos(struct rogue_ubo_data *ubo_data) -{ - unsigned shareds = 0; - - for (unsigned u = 0; u < ubo_data->num_ubo_entries; ++u) { - /* Ensure there aren't any gaps. */ - assert(ubo_data->dest[u] == ~0); - - ubo_data->dest[u] = shareds; - shareds += ubo_data->size[u]; - } - - return shareds; -} - -/** - * \brief Reserves a UBO and calculates its data. - * - * \param[in] ubo_data The UBO data. - * \param[in] desc_set The UBO descriptor set. - * \param[in] binding The UBO binding. - * \param[in] size The size required by the UBO (in dwords). - */ -static void reserve_ubo(struct rogue_ubo_data *ubo_data, - unsigned desc_set, - unsigned binding, - unsigned size) -{ - unsigned i = ubo_data->num_ubo_entries; - assert(i < ARRAY_SIZE(ubo_data->desc_set)); - - ubo_data->desc_set[i] = desc_set; - ubo_data->binding[i] = binding; - ubo_data->dest[i] = ~0; - ubo_data->size[i] = size; - ++ubo_data->num_ubo_entries; -} - -/** - * \brief Collects UBO data to feed-back to the driver. - * - * \param[in] common_data Common build data. - * \param[in] nir NIR shader. - */ -static void collect_ubo_data(struct rogue_common_build_data *common_data, - nir_shader *nir) -{ - /* Iterate over each UBO. */ - nir_foreach_variable_with_modes (var, nir, nir_var_mem_ubo) { - unsigned desc_set = var->data.driver_location; - unsigned binding = var->data.binding; - unsigned ubo_size_regs = 0; - - nir_function_impl *entry = nir_shader_get_entrypoint(nir); - /* Iterate over each load_ubo that uses this UBO. */ - nir_foreach_block (block, entry) { - nir_foreach_instr (instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); - if (intr->intrinsic != nir_intrinsic_load_ubo) - continue; - - assert(nir_src_num_components(intr->src[0]) == 1); - assert(nir_src_num_components(intr->src[1]) == 1); - - unsigned load_desc_set = nir_src_comp_as_uint(intr->src[0], 0); - unsigned load_binding = nir_src_comp_as_uint(intr->src[1], 0); - if (load_desc_set != desc_set || load_binding != binding) - continue; - - ASSERTED unsigned size_bytes = nir_intrinsic_range(intr); - assert(size_bytes == ROGUE_REG_SIZE_BYTES); - - unsigned offset_bytes = nir_intrinsic_range_base(intr); - assert(!(offset_bytes % ROGUE_REG_SIZE_BYTES)); - - unsigned offset_regs = offset_bytes / ROGUE_REG_SIZE_BYTES; - - /* TODO: Put offsets in a BITSET_DECLARE and check for gaps. */ - - /* Find the largest load offset. */ - ubo_size_regs = MAX2(ubo_size_regs, offset_regs); - } - } - - /* UBO size = largest offset + 1. */ - ++ubo_size_regs; - - reserve_ubo(&common_data->ubo_data, desc_set, binding, ubo_size_regs); - } - - common_data->shareds = alloc_ubos(&common_data->ubo_data); - assert(common_data->shareds < rogue_reg_infos[ROGUE_REG_CLASS_SHARED].num); -} - /** * \brief Collects I/O data to feed-back to the driver. * @@ -482,9 +379,6 @@ void rogue_collect_io_data(struct rogue_build_ctx *ctx, nir_shader *nir) gl_shader_stage stage = nir->info.stage; struct rogue_common_build_data *common_data = &ctx->common_data[stage]; - /* Collect stage-agnostic data. */ - collect_ubo_data(common_data, nir); - /* Collect stage-specific data. */ switch (stage) { case MESA_SHADER_FRAGMENT: @@ -566,41 +460,3 @@ unsigned rogue_output_index_vs(struct rogue_vertex_outputs *outputs, return outputs->base[i] + component; } - -/** - * \brief Returns the allocated shared register index for a given UBO offset. - * - * \param[in] ubo_data The UBO data. - * \param[in] desc_set The UBO descriptor set. - * \param[in] binding The UBO binding. - * \param[in] offset_bytes The UBO offset in bytes. - * \return The UBO offset shared register index. - */ -PUBLIC -unsigned rogue_ubo_reg(struct rogue_ubo_data *ubo_data, - unsigned desc_set, - unsigned binding, - unsigned offset_bytes) -{ - unsigned ubo_index = ~0; - unsigned offset_regs; - - /* Find UBO located at (desc_set, binding). */ - for (unsigned u = 0; u < ubo_data->num_ubo_entries; ++u) { - if (ubo_data->dest[u] == ~0) - continue; - - if (ubo_data->desc_set[u] != desc_set || ubo_data->binding[u] != binding) - continue; - - ubo_index = u; - break; - } - - assert(ubo_index != ~0); - - assert(!(offset_bytes % ROGUE_REG_SIZE_BYTES)); - offset_regs = offset_bytes / ROGUE_REG_SIZE_BYTES; - - return ubo_data->dest[ubo_index] + offset_regs; -} diff --git a/src/imagination/rogue/rogue_compile.c b/src/imagination/rogue/rogue_compile.c index aa06afb8c54..687557a9911 100644 --- a/src/imagination/rogue/rogue_compile.c +++ b/src/imagination/rogue/rogue_compile.c @@ -21,6 +21,7 @@ * SOFTWARE. */ +#include "compiler/shader_enums.h" #include "compiler/spirv/nir_spirv.h" #include "nir/nir.h" #include "rogue.h" @@ -271,19 +272,101 @@ static void trans_nir_intrinsic_store_output(rogue_builder *b, unreachable("Unimplemented NIR store_output variant."); } +static inline gl_shader_stage +pvr_stage_to_mesa(enum pvr_stage_allocation pvr_stage) +{ + switch (pvr_stage) { + case PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY: + return MESA_SHADER_VERTEX; + + case PVR_STAGE_ALLOCATION_FRAGMENT: + return MESA_SHADER_FRAGMENT; + + case PVR_STAGE_ALLOCATION_COMPUTE: + return MESA_SHADER_COMPUTE; + + default: + break; + } + + unreachable("Unsupported pvr_stage_allocation."); +} + +static inline enum pvr_stage_allocation +mesa_stage_to_pvr(gl_shader_stage mesa_stage) +{ + switch (mesa_stage) { + case MESA_SHADER_VERTEX: + return PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY; + + case MESA_SHADER_FRAGMENT: + return PVR_STAGE_ALLOCATION_FRAGMENT; + + case MESA_SHADER_COMPUTE: + return PVR_STAGE_ALLOCATION_COMPUTE; + + default: + break; + } + + unreachable("Unsupported gl_shader_stage."); +} + static void trans_nir_intrinsic_load_vulkan_descriptor(rogue_builder *b, nir_intrinsic_instr *intr) { rogue_instr *instr; - /* unsigned desc_set = nir_src_comp_as_uint(intr->src[0], 0); */ - /* unsigned binding = nir_src_comp_as_uint(intr->src[0], 1); */ + unsigned desc_set = nir_src_comp_as_uint(intr->src[0], 0); + unsigned binding = nir_src_comp_as_uint(intr->src[0], 1); ASSERTED VkDescriptorType desc_type = nir_src_comp_as_uint(intr->src[0], 2); assert(desc_type == nir_intrinsic_desc_type(intr)); + struct pvr_pipeline_layout *pipeline_layout = + b->shader->ctx->pipeline_layout; + + /* Defaults for offline compiler. */ + /* TODO: Load these from an offline pipeline description + * if using the offline compiler. + */ + unsigned desc_set_table_sh_reg = 0; + unsigned flat_desc_idx = binding; + + if (pipeline_layout) { + /* Fetch shared registers containing descriptor set table address. */ + enum pvr_stage_allocation pvr_stage = mesa_stage_to_pvr(b->shader->stage); + assert(pipeline_layout->sh_reg_layout_per_stage[pvr_stage] + .descriptor_set_addrs_table.present); + desc_set_table_sh_reg = + pipeline_layout->sh_reg_layout_per_stage[pvr_stage] + .descriptor_set_addrs_table.offset; + + /* Lookup offsets for descriptor set and descriptor. */ + assert(desc_set < pipeline_layout->set_count); + + unsigned binding_count = + pipeline_layout->set_layout[desc_set]->binding_count; + assert(binding < binding_count); + + flat_desc_idx = ~0U; + for (unsigned u = 0; u < binding_count; ++u) { + unsigned binding_number = + pipeline_layout->set_layout[desc_set]->bindings[u].binding_number; + + if (binding_number == binding) { + flat_desc_idx = pipeline_layout->set_layout[desc_set] + ->bindings[u] + .descriptor_index; + assert(pipeline_layout->set_layout[desc_set]->bindings[u].type == + desc_type); + break; + } + } + assert(flat_desc_idx != ~0U); + } + unsigned desc_set_table_addr_idx = b->shader->ctx->next_ssa_idx++; - rogue_regarray *desc_set_table_addr_64 = - rogue_ssa_vec_regarray(b->shader, 2, desc_set_table_addr_idx, 0); + rogue_ssa_vec_regarray(b->shader, 2, desc_set_table_addr_idx, 0); rogue_regarray *desc_set_table_addr_2x32[2] = { rogue_ssa_vec_regarray(b->shader, 1, desc_set_table_addr_idx, 0), rogue_ssa_vec_regarray(b->shader, 1, desc_set_table_addr_idx, 1), @@ -291,28 +374,73 @@ trans_nir_intrinsic_load_vulkan_descriptor(rogue_builder *b, instr = &rogue_MOV(b, rogue_ref_regarray(desc_set_table_addr_2x32[0]), - rogue_ref_reg(rogue_shared_reg(b->shader, 0))) + rogue_ref_reg( + rogue_shared_reg(b->shader, desc_set_table_sh_reg))) ->instr; rogue_add_instr_comment(instr, "desc_set_table_addr_lo"); - instr = &rogue_MOV(b, - rogue_ref_regarray(desc_set_table_addr_2x32[1]), - rogue_ref_reg(rogue_shared_reg(b->shader, 1))) - ->instr; + instr = + &rogue_MOV( + b, + rogue_ref_regarray(desc_set_table_addr_2x32[1]), + rogue_ref_reg(rogue_shared_reg(b->shader, desc_set_table_sh_reg + 1))) + ->instr; rogue_add_instr_comment(instr, "desc_set_table_addr_hi"); - /* TODO NEXT: Just using offset 0 for both the descriptor table and the entry - * (UBO), but need to calculate this from desc_set and binding. */ + /* TODO: Don't add offsets if the descriptor set/flat descriptor is 0. */ + + /* Offset the descriptor set table address to access the descriptor set. */ + unsigned desc_set_table_addr_offset_idx = b->shader->ctx->next_ssa_idx++; + rogue_regarray *desc_set_table_addr_offset_64 = + rogue_ssa_vec_regarray(b->shader, 2, desc_set_table_addr_offset_idx, 0); + rogue_regarray *desc_set_table_addr_offset_2x32[2] = { + rogue_ssa_vec_regarray(b->shader, 1, desc_set_table_addr_offset_idx, 0), + rogue_ssa_vec_regarray(b->shader, 1, desc_set_table_addr_offset_idx, 1), + }; + + rogue_ADD64(b, + rogue_ref_regarray(desc_set_table_addr_offset_2x32[0]), + rogue_ref_regarray(desc_set_table_addr_offset_2x32[1]), + rogue_ref_io(ROGUE_IO_NONE), + rogue_ref_regarray(desc_set_table_addr_2x32[0]), + rogue_ref_regarray(desc_set_table_addr_2x32[1]), + rogue_ref_imm(desc_set * 4), /* TODO: use UMADD64 instead */ + rogue_ref_imm(0), + rogue_ref_io(ROGUE_IO_NONE)); + unsigned desc_set_addr_idx = b->shader->ctx->next_ssa_idx++; rogue_regarray *desc_set_addr_64 = rogue_ssa_vec_regarray(b->shader, 2, desc_set_addr_idx, 0); + rogue_regarray *desc_set_addr_2x32[2] = { + rogue_ssa_vec_regarray(b->shader, 1, desc_set_addr_idx, 0), + rogue_ssa_vec_regarray(b->shader, 1, desc_set_addr_idx, 1), + }; instr = &rogue_LD(b, rogue_ref_regarray(desc_set_addr_64), rogue_ref_drc(0), rogue_ref_val(2), - rogue_ref_regarray(desc_set_table_addr_64)) + rogue_ref_regarray(desc_set_table_addr_offset_64)) ->instr; rogue_add_instr_comment(instr, "load descriptor set"); + /* Offset the descriptor set address to access the descriptor. */ + unsigned desc_addr_offset_idx = b->shader->ctx->next_ssa_idx++; + rogue_regarray *desc_addr_offset_64 = + rogue_ssa_vec_regarray(b->shader, 2, desc_addr_offset_idx, 0); + rogue_regarray *desc_addr_offset_2x32[2] = { + rogue_ssa_vec_regarray(b->shader, 1, desc_addr_offset_idx, 0), + rogue_ssa_vec_regarray(b->shader, 1, desc_addr_offset_idx, 1), + }; + + rogue_ADD64(b, + rogue_ref_regarray(desc_addr_offset_2x32[0]), + rogue_ref_regarray(desc_addr_offset_2x32[1]), + rogue_ref_io(ROGUE_IO_NONE), + rogue_ref_regarray(desc_set_addr_2x32[0]), + rogue_ref_regarray(desc_set_addr_2x32[1]), + rogue_ref_imm(flat_desc_idx * 4), /* TODO: use UMADD64 instead */ + rogue_ref_imm(0), + rogue_ref_io(ROGUE_IO_NONE)); + unsigned desc_addr_idx = intr->dest.ssa.index; rogue_regarray *desc_addr_64 = rogue_ssa_vec_regarray(b->shader, 2, desc_addr_idx, 0); @@ -320,7 +448,7 @@ trans_nir_intrinsic_load_vulkan_descriptor(rogue_builder *b, rogue_ref_regarray(desc_addr_64), rogue_ref_drc(0), rogue_ref_val(2), - rogue_ref_regarray(desc_set_addr_64)) + rogue_ref_regarray(desc_addr_offset_64)) ->instr; rogue_add_instr_comment(instr, "load descriptor"); } diff --git a/src/imagination/rogue/rogue_info.c b/src/imagination/rogue/rogue_info.c index ae11b126e1f..ad4157dce11 100644 --- a/src/imagination/rogue/rogue_info.c +++ b/src/imagination/rogue/rogue_info.c @@ -424,8 +424,8 @@ const rogue_alu_op_info rogue_alu_op_infos[ROGUE_ALU_OP_COUNT] = { .supported_src_types = { [0] = T(REG) | T(REGARRAY), [1] = T(REG) | T(REGARRAY), - [2] = T(REG) | T(REGARRAY), - [3] = T(REG) | T(REGARRAY)| T(IO), + [2] = T(REG) | T(REGARRAY) | T(IMM), + [3] = T(REG) | T(REGARRAY)| T(IO) | T(IMM), [4] = T(IO), }, }, diff --git a/src/imagination/rogue/tools/vk_compiler.c b/src/imagination/rogue/tools/vk_compiler.c index 73c0723bd1a..7011d1f557a 100644 --- a/src/imagination/rogue/tools/vk_compiler.c +++ b/src/imagination/rogue/tools/vk_compiler.c @@ -192,7 +192,7 @@ int main(int argc, char *argv[]) } /* Create build context. */ - ctx = rogue_build_context_create(compiler); + ctx = rogue_build_context_create(compiler, NULL); if (!ctx) { fprintf(stderr, "Failed to set up build context.\n"); goto err_destroy_compiler; diff --git a/src/imagination/vulkan/pvr_common.h b/src/imagination/vulkan/pvr_common.h index b7ade78b9de..01cac1ed15a 100644 --- a/src/imagination/vulkan/pvr_common.h +++ b/src/imagination/vulkan/pvr_common.h @@ -324,6 +324,23 @@ struct pvr_descriptor_state { uint32_t valid_mask; }; +/** + * \brief Indicates the layout of shared registers allocated by the driver. + * + * 'present' fields indicate if a certain resource was allocated for, and + * whether it will be present in the shareds. + * 'offset' fields indicate at which shared reg the resource starts at. + */ +struct pvr_sh_reg_layout { + /* If this is present, it will always take up 2 sh regs in size and contain + * the device address of the descriptor set addrs table. + */ + struct { + bool present; + uint32_t offset; + } descriptor_set_addrs_table; +}; + struct pvr_pipeline_layout { struct vk_object_base base; @@ -359,6 +376,9 @@ struct pvr_pipeline_layout { register_layout_in_dwords_per_stage[PVR_STAGE_ALLOCATION_COUNT] [PVR_MAX_DESCRIPTOR_SETS]; + /* TODO: Consider whether this needs to be here. */ + struct pvr_sh_reg_layout sh_reg_layout_per_stage[PVR_STAGE_ALLOCATION_COUNT]; + /* All sizes in dwords. */ struct pvr_pipeline_layout_reg_info { uint32_t primary_dynamic_size_in_dwords; diff --git a/src/imagination/vulkan/pvr_pipeline.c b/src/imagination/vulkan/pvr_pipeline.c index 0c88aa5bc9c..a319c97b2e0 100644 --- a/src/imagination/vulkan/pvr_pipeline.c +++ b/src/imagination/vulkan/pvr_pipeline.c @@ -647,23 +647,6 @@ static VkResult pvr_pds_descriptor_program_setup_buffers( return VK_SUCCESS; } -/** - * \brief Indicates the layout of shared registers allocated by the driver. - * - * 'present' fields indicate if a certain resource was allocated for, and - * whether it will be present in the shareds. - * 'offset' fields indicate at which shared reg the resource starts at. - */ -struct pvr_sh_reg_layout { - /* If this is present, it will always take up 2 sh regs in size and contain - * the device address of the descriptor set addrs table. - */ - struct { - bool present; - uint32_t offset; - } descriptor_set_addrs_table; -}; - static VkResult pvr_pds_descriptor_program_create_and_upload( struct pvr_device *const device, const VkAllocationCallbacks *const allocator, @@ -1150,11 +1133,13 @@ static VkResult pvr_compute_pipeline_compile( const VkAllocationCallbacks *const allocator, struct pvr_compute_pipeline *const compute_pipeline) { + struct pvr_pipeline_layout *layout = compute_pipeline->base.layout; + struct pvr_sh_reg_layout *sh_reg_layout = + &layout->sh_reg_layout_per_stage[PVR_STAGE_ALLOCATION_COMPUTE]; struct rogue_compile_time_consts_data compile_time_consts_data; uint32_t work_group_input_regs[PVR_WORKGROUP_DIMENSIONS]; struct pvr_explicit_constant_usage explicit_const_usage; uint32_t local_input_regs[PVR_WORKGROUP_DIMENSIONS]; - struct pvr_sh_reg_layout sh_reg_layout; struct rogue_ubo_data ubo_data; uint32_t barrier_coefficient; uint32_t usc_temps; @@ -1197,11 +1182,10 @@ static VkResult pvr_compute_pipeline_compile( } else { uint32_t sh_count; - sh_count = pvr_pipeline_alloc_shareds(device, - compute_pipeline->base.layout, + layout, PVR_STAGE_ALLOCATION_COMPUTE, - &sh_reg_layout); + sh_reg_layout); compute_pipeline->shader_state.const_shared_reg_count = sh_count; @@ -1216,9 +1200,9 @@ static VkResult pvr_compute_pipeline_compile( &compile_time_consts_data, &ubo_data, &explicit_const_usage, - compute_pipeline->base.layout, + layout, PVR_STAGE_ALLOCATION_COMPUTE, - &sh_reg_layout, + sh_reg_layout, &compute_pipeline->descriptor_state); if (result != VK_SUCCESS) goto err_free_shader; @@ -1523,6 +1507,11 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, }; static uint32_t hard_code_pipeline_n = 0; + struct pvr_pipeline_layout *layout = gfx_pipeline->base.layout; + struct pvr_sh_reg_layout *sh_reg_layout_vert = + &layout->sh_reg_layout_per_stage[PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY]; + struct pvr_sh_reg_layout *sh_reg_layout_frag = + &layout->sh_reg_layout_per_stage[PVR_STAGE_ALLOCATION_FRAGMENT]; const VkPipelineVertexInputStateCreateInfo *const vertex_input_state = pCreateInfo->pVertexInputState; const uint32_t cache_line_size = @@ -1535,29 +1524,21 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, pvr_hard_code_shader_required(&device->pdevice->dev_info); /* Vars needed for the new path. */ - /* TODO: These need to be passed into the compiler so that it knows which - * shared regs to use to access specific resources. - */ - struct pvr_sh_reg_layout vert_sh_reg_layout; - struct pvr_sh_reg_layout frag_sh_reg_layout; - uint32_t vert_sh_count = 0; - uint32_t frag_sh_count = 0; + uint32_t sh_count[PVR_STAGE_ALLOCATION_COUNT] = { 0 }; - if (!old_path) { - vert_sh_count = - pvr_pipeline_alloc_shareds(device, - gfx_pipeline->base.layout, - PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY, - &vert_sh_reg_layout); - - frag_sh_count = pvr_pipeline_alloc_shareds(device, - gfx_pipeline->base.layout, - PVR_STAGE_ALLOCATION_FRAGMENT, - &frag_sh_reg_layout); - } + if (!old_path) + for (enum pvr_stage_allocation pvr_stage = + PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY; + pvr_stage < PVR_STAGE_ALLOCATION_COMPUTE; + ++pvr_stage) + sh_count[pvr_stage] = pvr_pipeline_alloc_shareds( + device, + layout, + pvr_stage, + &layout->sh_reg_layout_per_stage[pvr_stage]); /* Setup shared build context. */ - ctx = rogue_build_context_create(compiler); + ctx = rogue_build_context_create(compiler, layout); if (!ctx) return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY); @@ -1667,7 +1648,8 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, * returning the sh count since the driver is in charge of allocating * them. */ - vertex_state->stage_state.const_shared_reg_count = vert_sh_count; + vertex_state->stage_state.const_shared_reg_count = + sh_count[PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY]; } } @@ -1698,7 +1680,8 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, * returning the sh count since the driver is in charge of allocating * them. */ - fragment_state->stage_state.const_shared_reg_count = frag_sh_count; + fragment_state->stage_state.const_shared_reg_count = + sh_count[PVR_STAGE_ALLOCATION_FRAGMENT]; } } @@ -1752,9 +1735,9 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, &ctx->common_data[MESA_SHADER_VERTEX].compile_time_consts_data, &ctx->common_data[MESA_SHADER_VERTEX].ubo_data, &vert_explicit_const_usage, - gfx_pipeline->base.layout, + layout, PVR_STAGE_ALLOCATION_VERTEX_GEOMETRY, - &vert_sh_reg_layout, + sh_reg_layout_vert, &gfx_pipeline->shader_state.vertex.descriptor_state); if (result != VK_SUCCESS) goto err_free_vertex_attrib_program; @@ -1775,9 +1758,9 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device, &ctx->common_data[MESA_SHADER_FRAGMENT].compile_time_consts_data, &ctx->common_data[MESA_SHADER_FRAGMENT].ubo_data, &frag_explicit_const_usage, - gfx_pipeline->base.layout, + layout, PVR_STAGE_ALLOCATION_FRAGMENT, - &frag_sh_reg_layout, + sh_reg_layout_frag, &gfx_pipeline->shader_state.fragment.descriptor_state); if (result != VK_SUCCESS) goto err_free_vertex_descriptor_program;