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intel/fs/gen12: Use TCS 8_PATCH mode.

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Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Kenneth Graunke
2019-05-03 16:39:18 -07:00
committed by Francisco Jerez
parent c92fb60007
commit 44754279ac
2 changed files with 8 additions and 6 deletions
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3
src/intel/compiler/brw_compiler.c
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@@ -101,7 +101,8 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
compiler->use_tcs_8_patch =
devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH);
devinfo->gen >= 12 ||
(devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH));
if (devinfo->gen >= 10) {
/* We don't support vec4 mode on Cannonlake. */

11
src/intel/compiler/brw_vec4_tcs.cpp
View File

@@ -360,12 +360,13 @@ brw_compile_tcs(const struct brw_compiler *compiler,
nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID);
if (compiler->use_tcs_8_patch &&
nir->info.tess.tcs_vertices_out <= 16 &&
nir->info.tess.tcs_vertices_out <= (devinfo->gen >= 12 ? 32 : 16) &&
2 + has_primitive_id + key->input_vertices <= 31) {
/* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First,
* the "Instance" field limits the number of output vertices to [1, 16].
* Secondly, the "Dispatch GRF Start Register for URB Data" field is
* limited to [0, 31] - which imposes a limit on the input vertices.
/* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the
* "Instance" field limits the number of output vertices to [1, 16] on
* gen11 and below, or [1, 32] on gen12 and above. Secondly, the
* "Dispatch GRF Start Register for URB Data" field is limited to [0,
* 31] - which imposes a limit on the input vertices.
*/
vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH;
prog_data->instances = nir->info.tess.tcs_vertices_out;