intel/compiler: Delete abs/neg handling in fsign code

This should have gone away when removing source modifiers.  They won't
be set any longer, so this is simply dead code.

Fixes: b7c47c4f7c ("intel/compiler: Drop nir_lower_to_source_mods() and related handling.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4691>
This commit is contained in:
Kenneth Graunke
2020-04-21 23:50:46 -07:00
parent 220f0e10d8
commit 4459a70a6e
2 changed files with 2 additions and 40 deletions

View File

@@ -879,35 +879,9 @@ fs_visitor::emit_fsign(const fs_builder &bld, const nir_alu_instr *instr,
}
op[0] = offset(op[0], bld, fsign_instr->src[0].swizzle[channel]);
/* Resolve any source modifiers. We could do slightly better on Gen8+
* if the only source modifier is negation, but *shrug*.
*/
if (op[1].negate || op[1].abs) {
fs_reg tmp = bld.vgrf(op[1].type);
bld.MOV(tmp, op[1]);
op[1] = tmp;
}
}
if (op[0].abs) {
/* Straightforward since the source can be assumed to be either strictly
* >= 0 or strictly <= 0 depending on the setting of the negate flag.
*/
set_condmod(BRW_CONDITIONAL_NZ, bld.MOV(result, op[0]));
if (instr->op == nir_op_fsign) {
inst = (op[0].negate)
? bld.MOV(result, brw_imm_f(-1.0f))
: bld.MOV(result, brw_imm_f(1.0f));
} else {
op[1].negate = (op[0].negate != op[1].negate);
inst = bld.MOV(result, op[1]);
}
set_predicate(BRW_PREDICATE_NORMAL, inst);
} else if (type_sz(op[0].type) == 2) {
if (type_sz(op[0].type) == 2) {
/* AND(val, 0x8000) gives the sign bit.
*
* Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.

View File

@@ -1788,19 +1788,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
unreachable("not reached: should have been lowered");
case nir_op_fsign:
if (op[0].abs) {
/* Straightforward since the source can be assumed to be either
* strictly >= 0 or strictly <= 0 depending on the setting of the
* negate flag.
*/
inst = emit(MOV(dst, op[0]));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
inst = (op[0].negate)
? emit(MOV(dst, brw_imm_f(-1.0f)))
: emit(MOV(dst, brw_imm_f(1.0f)));
inst->predicate = BRW_PREDICATE_NORMAL;
} else if (type_sz(op[0].type) < 8) {
if (type_sz(op[0].type) < 8) {
/* AND(val, 0x80000000) gives the sign bit.
*
* Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not