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radeonsi: simplify binning settings to work around GPU hangs

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22084>
This commit is contained in:
Marek Olšák
2023-03-22 12:22:59 -04:00
committed by Marge Bot
parent 281126f1d6
commit 43dc19f44d
1 changed files with 7 additions and 17 deletions
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24
src/gallium/drivers/radeonsi/si_pipe.c
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@@ -1359,23 +1359,13 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
sscreen->debug_flags & DBG(DPBB));
if (sscreen->dpbb_allowed) {
if (sscreen->info.has_dedicated_vram && sscreen->info.max_render_backends > 4) {
sscreen->pbb_context_states_per_bin = 1;
sscreen->pbb_persistent_states_per_bin = 1;
} else {
/* This is a workaround for:
* https://bugs.freedesktop.org/show_bug.cgi?id=110214
* (an alternative is to insert manual BATCH_BREAK event when
* a context_roll is detected). */
sscreen->pbb_context_states_per_bin = sscreen->info.has_gfx9_scissor_bug ? 1 : 3;
sscreen->pbb_persistent_states_per_bin = 8;
}
if (!sscreen->info.has_gfx9_scissor_bug)
sscreen->pbb_context_states_per_bin =
debug_get_num_option("AMD_DEBUG_DPBB_CS", sscreen->pbb_context_states_per_bin);
sscreen->pbb_persistent_states_per_bin =
debug_get_num_option("AMD_DEBUG_DPBB_PS", sscreen->pbb_persistent_states_per_bin);
/* Only bin draws that have no CONTEXT and SH register changes between them because higher
* settings cause hangs. We've only been able to reproduce hangs on smaller chips
* (e.g. Navi24, GFX1103), though all chips might have them. What we see may be due to
* a driver bug.
*/
sscreen->pbb_context_states_per_bin = 1;
sscreen->pbb_persistent_states_per_bin = 1;
assert(sscreen->pbb_context_states_per_bin >= 1 &&
sscreen->pbb_context_states_per_bin <= 6);