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intel/compiler: Convert brw_wm_aa_enable to brw_sometimes

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There are other cases where we want a tri-state logic like this.  May as
well have one enum for all the cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
This commit is contained in:
Jason Ekstrand
2021-11-19 11:57:03 -06:00
committed by Marge Bot
parent 5d1c538449
commit 43ca7f4178
3 changed files with 14 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/gallium/drivers/crocus/crocus_state.c
View File

@@ -4810,23 +4810,23 @@ crocus_populate_fs_key(const struct crocus_context *ice,
key->stats_wm = ice->state.stats_wm; key->stats_wm = ice->state.stats_wm;
#endif #endif
uint32_t line_aa = BRW_WM_AA_NEVER; uint32_t line_aa = BRW_NEVER;
if (rast->cso.line_smooth) { if (rast->cso.line_smooth) {
int reduced_prim = ice->state.reduced_prim_mode; int reduced_prim = ice->state.reduced_prim_mode;
if (reduced_prim == PIPE_PRIM_LINES) if (reduced_prim == PIPE_PRIM_LINES)
line_aa = BRW_WM_AA_ALWAYS; line_aa = BRW_ALWAYS;
else if (reduced_prim == PIPE_PRIM_TRIANGLES) { else if (reduced_prim == PIPE_PRIM_TRIANGLES) {
if (rast->cso.fill_front == PIPE_POLYGON_MODE_LINE) { if (rast->cso.fill_front == PIPE_POLYGON_MODE_LINE) {
line_aa = BRW_WM_AA_SOMETIMES; line_aa = BRW_SOMETIMES;
if (rast->cso.fill_back == PIPE_POLYGON_MODE_LINE || if (rast->cso.fill_back == PIPE_POLYGON_MODE_LINE ||
rast->cso.cull_face == PIPE_FACE_BACK) rast->cso.cull_face == PIPE_FACE_BACK)
line_aa = BRW_WM_AA_ALWAYS; line_aa = BRW_ALWAYS;
} else if (rast->cso.fill_back == PIPE_POLYGON_MODE_LINE) { } else if (rast->cso.fill_back == PIPE_POLYGON_MODE_LINE) {
line_aa = BRW_WM_AA_SOMETIMES; line_aa = BRW_SOMETIMES;
if (rast->cso.cull_face == PIPE_FACE_FRONT) if (rast->cso.cull_face == PIPE_FACE_FRONT)
line_aa = BRW_WM_AA_ALWAYS; line_aa = BRW_ALWAYS;
} }
} }
} }

10
src/intel/compiler/brw_compiler.h
View File

@@ -458,10 +458,10 @@ enum brw_wm_iz_bits {
BRW_WM_IZ_BIT_MAX = 0x40 BRW_WM_IZ_BIT_MAX = 0x40
}; };
enum brw_wm_aa_enable { enum brw_sometimes {
BRW_WM_AA_NEVER, BRW_NEVER = 0,
BRW_WM_AA_SOMETIMES, BRW_SOMETIMES,
BRW_WM_AA_ALWAYS BRW_ALWAYS
}; };
/** The program key for Fragment/Pixel Shaders. */ /** The program key for Fragment/Pixel Shaders. */
@@ -494,7 +494,7 @@ struct brw_wm_prog_key {
bool persample_interp:1; bool persample_interp:1;
bool multisample_fbo:1; bool multisample_fbo:1;
enum brw_wm_aa_enable line_aa:2; enum brw_sometimes line_aa:2;
bool force_dual_color_blend:1; bool force_dual_color_blend:1;
bool coherent_fb_fetch:1; bool coherent_fb_fetch:1;
bool ignore_sample_mask_out:1; bool ignore_sample_mask_out:1;

6
src/intel/compiler/brw_fs_thread_payload.cpp
View File

@@ -284,7 +284,7 @@ static const struct {
}; };
/** /**
* \param line_aa BRW_WM_AA_NEVER, BRW_WM_AA_ALWAYS or BRW_WM_AA_SOMETIMES * \param line_aa BRW_NEVER, BRW_ALWAYS or BRW_SOMETIMES
* \param lookup bitmask of BRW_WM_IZ_* flags * \param lookup bitmask of BRW_WM_IZ_* flags
*/ */
static inline void static inline void
@@ -326,10 +326,10 @@ setup_fs_payload_gfx4(fs_thread_payload &payload,
if (wm_iz_table[lookup].sd_to_rt || kill_stats_promoted_workaround) if (wm_iz_table[lookup].sd_to_rt || kill_stats_promoted_workaround)
source_depth_to_render_target = true; source_depth_to_render_target = true;
if (wm_iz_table[lookup].ds_present || key->line_aa != BRW_WM_AA_NEVER) { if (wm_iz_table[lookup].ds_present || key->line_aa != BRW_NEVER) {
payload.aa_dest_stencil_reg[0] = reg; payload.aa_dest_stencil_reg[0] = reg;
runtime_check_aads_emit = runtime_check_aads_emit =
!wm_iz_table[lookup].ds_present && key->line_aa == BRW_WM_AA_SOMETIMES; !wm_iz_table[lookup].ds_present && key->line_aa == BRW_SOMETIMES;
reg++; reg++;
} }