intel/blorp/gen12: Set FWCC when storing the clear color.

From "Render Target Fast Clear" description for Gen12:

   "SW must store clear color using MI_STORE_DATA_IMM with
   ForceWriteCompletionCheck bit set."

From Instruction_MI_STORE_DATA_IMM, bitfield 10 (when set to 1):

   "Following the last write from this command, Command Streamer
   will wait for all previous writes are completed and in global
   observable domain before moving to next command."

We use 4 SDIs to store the clear color (one per channel). From the
description, it looks to me that setting that flag only on the last SDI
should be enough.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

src/intel/blorp/blorp_genX_exec.h

@@ -1785,6 +1785,10 @@ blorp_update_clear_color(struct blorp_batch *batch,
             sdi.Address = info->clear_color_addr;
             sdi.Address.offset += i * 4;
             sdi.ImmediateData = info->clear_color.u32[i];
+#if GEN_GEN >= 12
+            if (i == 3)
+               sdi.ForceWriteCompletionCheck = true;
+#endif
          }
       }
 #elif GEN_GEN >= 7

src/intel/genxml/gen12.xml

@@ -6179,6 +6179,7 @@
 
   <instruction name="MI_STORE_DATA_IMM" bias="2" length="4">
     <field name="DWord Length" start="0" end="9" type="uint" default="2"/>
+    <field name="Force Write Completion Check " start="10" end="10" type="bool"/>
     <field name="Store Qword" start="21" end="21" type="uint"/>
     <field name="Use Global GTT" start="22" end="22" type="bool"/>
     <field name="MI Command Opcode" start="23" end="28" type="uint" default="32"/>