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compiler: Rename local_size to workgroup_size

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Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11190>
This commit is contained in:
Caio Marcelo de Oliveira Filho
2021-05-26 23:53:32 -07:00
committed by Marge Bot
parent 4b9e52e818
commit 430d2206da
49 changed files with 286 additions and 286 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/intel/compiler/brw_fs.cpp
View File

@@ -9534,10 +9534,10 @@ lower_simd(nir_builder *b, nir_instr *instr, void *options)
/* If the whole workgroup fits in one thread, we can lower subgroup_id
* to a constant zero.
*/
if (!b->shader->info.cs.local_size_variable) {
unsigned local_workgroup_size = b->shader->info.cs.local_size[0] *
b->shader->info.cs.local_size[1] *
b->shader->info.cs.local_size[2];
if (!b->shader->info.cs.workgroup_size_variable) {
unsigned local_workgroup_size = b->shader->info.cs.workgroup_size[0] *
b->shader->info.cs.workgroup_size[1] *
b->shader->info.cs.workgroup_size[2];
if (local_workgroup_size <= simd_width)
return nir_imm_int(b, 0);
}
@@ -9599,15 +9599,15 @@ brw_compile_cs(const struct brw_compiler *compiler,
unsigned min_dispatch_width;
unsigned max_dispatch_width;
if (nir->info.cs.local_size_variable) {
if (nir->info.cs.workgroup_size_variable) {
generate_all = true;
min_dispatch_width = 8;
max_dispatch_width = 32;
} else {
generate_all = false;
prog_data->local_size[0] = nir->info.cs.local_size[0];
prog_data->local_size[1] = nir->info.cs.local_size[1];
prog_data->local_size[2] = nir->info.cs.local_size[2];
prog_data->local_size[0] = nir->info.cs.workgroup_size[0];
prog_data->local_size[1] = nir->info.cs.workgroup_size[1];
prog_data->local_size[2] = nir->info.cs.workgroup_size[2];
unsigned local_workgroup_size = prog_data->local_size[0] *
prog_data->local_size[1] *
prog_data->local_size[2];

8
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -113,7 +113,7 @@ fs_visitor::nir_setup_uniforms()
assert(uniforms == prog_data->nr_params);
uint32_t *param;
if (nir->info.cs.local_size_variable &&
if (nir->info.cs.workgroup_size_variable &&
compiler->lower_variable_group_size) {
param = brw_stage_prog_data_add_params(prog_data, 3);
for (unsigned i = 0; i < 3; i++) {
@@ -3671,7 +3671,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
* invocations are already executed lock-step. Instead of an actual
* barrier just emit a scheduling fence, that will generate no code.
*/
if (!nir->info.cs.local_size_variable &&
if (!nir->info.cs.workgroup_size_variable &&
workgroup_size() <= dispatch_width) {
bld.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE);
break;
@@ -3816,7 +3816,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
case nir_intrinsic_load_local_group_size: {
assert(compiler->lower_variable_group_size);
assert(nir->info.cs.local_size_variable);
assert(nir->info.cs.workgroup_size_variable);
for (unsigned i = 0; i < 3; i++) {
bld.MOV(retype(offset(dest, bld, i), BRW_REGISTER_TYPE_UD),
group_size[i]);
@@ -4324,7 +4324,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
*
* TODO: Check if applies for many HW threads sharing same Data Port.
*/
if (!nir->info.cs.local_size_variable &&
if (!nir->info.cs.workgroup_size_variable &&
slm_fence && workgroup_size() <= dispatch_width)
slm_fence = false;

34
src/intel/compiler/brw_nir_lower_cs_intrinsics.c
View File

@@ -81,13 +81,13 @@ lower_cs_intrinsics_convert_block(struct lower_intrinsics_state *state,
nir_ssa_def *size_x;
nir_ssa_def *size_y;
if (state->nir->info.cs.local_size_variable) {
if (state->nir->info.cs.workgroup_size_variable) {
nir_ssa_def *size_xyz = nir_load_local_group_size(b);
size_x = nir_channel(b, size_xyz, 0);
size_y = nir_channel(b, size_xyz, 1);
} else {
size_x = nir_imm_int(b, nir->info.cs.local_size[0]);
size_y = nir_imm_int(b, nir->info.cs.local_size[1]);
size_x = nir_imm_int(b, nir->info.cs.workgroup_size[0]);
size_y = nir_imm_int(b, nir->info.cs.workgroup_size[1]);
}
nir_ssa_def *size_xy = nir_imul(b, size_x, size_y);
@@ -120,8 +120,8 @@ lower_cs_intrinsics_convert_block(struct lower_intrinsics_state *state,
id_x = nir_umod(b, linear, size_x);
id_y = nir_umod(b, nir_udiv(b, linear, size_x), size_y);
local_index = linear;
} else if (!nir->info.cs.local_size_variable &&
nir->info.cs.local_size[1] % 4 == 0) {
} else if (!nir->info.cs.workgroup_size_variable &&
nir->info.cs.workgroup_size[1] % 4 == 0) {
/* 1x4 block X-major lid order. Same as X-major except increments in
* blocks of width=1 height=4. Always optimal for tileY and usually
* optimal for linear accesses.
@@ -213,16 +213,16 @@ lower_cs_intrinsics_convert_block(struct lower_intrinsics_state *state,
case nir_intrinsic_load_num_subgroups: {
nir_ssa_def *size;
if (state->nir->info.cs.local_size_variable) {
if (state->nir->info.cs.workgroup_size_variable) {
nir_ssa_def *size_xyz = nir_load_local_group_size(b);
nir_ssa_def *size_x = nir_channel(b, size_xyz, 0);
nir_ssa_def *size_y = nir_channel(b, size_xyz, 1);
nir_ssa_def *size_z = nir_channel(b, size_xyz, 2);
size = nir_imul(b, nir_imul(b, size_x, size_y), size_z);
} else {
size = nir_imm_int(b, nir->info.cs.local_size[0] *
nir->info.cs.local_size[1] *
nir->info.cs.local_size[2]);
size = nir_imm_int(b, nir->info.cs.workgroup_size[0] *
nir->info.cs.workgroup_size[1] *
nir->info.cs.workgroup_size[2]);
}
/* Calculate the equivalent of DIV_ROUND_UP. */
@@ -273,16 +273,16 @@ brw_nir_lower_cs_intrinsics(nir_shader *nir)
};
/* Constraints from NV_compute_shader_derivatives. */
if (!nir->info.cs.local_size_variable) {
if (!nir->info.cs.workgroup_size_variable) {
if (nir->info.cs.derivative_group == DERIVATIVE_GROUP_QUADS) {
assert(nir->info.cs.local_size[0] % 2 == 0);
assert(nir->info.cs.local_size[1] % 2 == 0);
assert(nir->info.cs.workgroup_size[0] % 2 == 0);
assert(nir->info.cs.workgroup_size[1] % 2 == 0);
} else if (nir->info.cs.derivative_group == DERIVATIVE_GROUP_LINEAR) {
ASSERTED unsigned local_workgroup_size =
nir->info.cs.local_size[0] *
nir->info.cs.local_size[1] *
nir->info.cs.local_size[2];
assert(local_workgroup_size % 4 == 0);
ASSERTED unsigned workgroup_size =
nir->info.cs.workgroup_size[0] *
nir->info.cs.workgroup_size[1] *
nir->info.cs.workgroup_size[2];
assert(workgroup_size % 4 == 0);
}
}

2
src/intel/compiler/brw_nir_rt.c
View File

@@ -426,7 +426,7 @@ brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler,
"RT Ray-Gen Trampoline");
ralloc_steal(mem_ctx, b.shader);
b.shader->info.cs.local_size_variable = true;
b.shader->info.cs.workgroup_size_variable = true;
/* The RT global data and raygen BINDLESS_SHADER_RECORD addresses are
* passed in as push constants in the first register. We deal with the