anv: Refactor pipeline l3 config setup
Now that we're using gen_l3_config.c, we no longer have one set of l3 config functions per gen and we can simplify a bit. Also, we know that only compute uses SLM so we don't need to look for it in all of the stages. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
@@ -44,8 +44,6 @@ void genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer);
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void genX(flush_pipeline_select_3d)(struct anv_cmd_buffer *cmd_buffer);
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void genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer);
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void genX(setup_pipeline_l3_config)(struct anv_pipeline *pipeline);
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void genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
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const struct anv_pipeline *pipeline);
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@@ -28,6 +28,7 @@
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#include <fcntl.h>
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#include "util/mesa-sha1.h"
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#include "common/gen_l3_config.h"
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#include "anv_private.h"
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#include "brw_nir.h"
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#include "anv_nir.h"
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@@ -802,29 +803,6 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
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return VK_SUCCESS;
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}
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void
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anv_setup_pipeline_l3_config(struct anv_pipeline *pipeline)
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{
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const struct gen_device_info *devinfo = &pipeline->device->info;
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switch (devinfo->gen) {
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case 7:
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if (devinfo->is_haswell)
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gen75_setup_pipeline_l3_config(pipeline);
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else
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gen7_setup_pipeline_l3_config(pipeline);
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break;
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case 8:
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gen8_setup_pipeline_l3_config(pipeline);
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break;
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case 9:
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gen9_setup_pipeline_l3_config(pipeline);
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break;
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default:
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unreachable("unsupported gen\n");
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}
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}
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void
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anv_compute_urb_partition(struct anv_pipeline *pipeline)
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{
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@@ -1151,6 +1129,26 @@ anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
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}
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}
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/**
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* Calculate the desired L3 partitioning based on the current state of the
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* pipeline. For now this simply returns the conservative defaults calculated
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* by get_default_l3_weights(), but we could probably do better by gathering
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* more statistics from the pipeline state (e.g. guess of expected URB usage
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* and bound surfaces), or by using feed-back from performance counters.
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*/
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void
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anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
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{
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const struct gen_device_info *devinfo = &pipeline->device->info;
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const struct gen_l3_weights w =
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gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
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pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
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pipeline->urb.total_size =
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gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
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}
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VkResult
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anv_pipeline_init(struct anv_pipeline *pipeline,
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struct anv_device *device,
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@@ -1243,7 +1241,7 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
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assert(extra->disable_vs);
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}
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anv_setup_pipeline_l3_config(pipeline);
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anv_pipeline_setup_l3_config(pipeline, false);
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anv_compute_urb_partition(pipeline);
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const VkPipelineVertexInputStateCreateInfo *vi_info =
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@@ -1648,7 +1648,7 @@ void
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anv_compute_urb_partition(struct anv_pipeline *pipeline);
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void
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anv_setup_pipeline_l3_config(struct anv_pipeline *pipeline);
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anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
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/**
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* Subsurface of an anv_image.
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@@ -27,33 +27,6 @@
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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/**
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* Calculate the desired L3 partitioning based on the current state of the
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* pipeline. For now this simply returns the conservative defaults calculated
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* by get_default_l3_weights(), but we could probably do better by gathering
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* more statistics from the pipeline state (e.g. guess of expected URB usage
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* and bound surfaces), or by using feed-back from performance counters.
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*/
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static struct gen_l3_weights
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get_pipeline_state_l3_weights(const struct anv_pipeline *pipeline)
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{
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bool needs_dc = false, needs_slm = false;
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for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
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if (!anv_pipeline_has_stage(pipeline, i))
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continue;
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const struct brw_stage_prog_data *prog_data =
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anv_shader_bin_get_prog_data(pipeline->shaders[i]);
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needs_dc |= pipeline->needs_data_cache;
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needs_slm |= prog_data->total_shared;
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}
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return gen_get_default_l3_weights(&pipeline->device->info,
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needs_dc, needs_slm);
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}
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#define emit_lri(batch, reg, imm) \
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anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { \
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lri.RegisterOffset = __anv_reg_num(reg); \
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@@ -207,17 +180,6 @@ setup_l3_config(struct anv_cmd_buffer *cmd_buffer/*, struct brw_context *brw*/,
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}
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void
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genX(setup_pipeline_l3_config)(struct anv_pipeline *pipeline)
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{
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const struct gen_l3_weights w = get_pipeline_state_l3_weights(pipeline);
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const struct gen_device_info *devinfo = &pipeline->device->info;
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pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
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pipeline->urb.total_size =
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gen_get_l3_config_urb_size(devinfo, pipeline->urb.l3_config);
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}
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void
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genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
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const struct anv_pipeline *pipeline)
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@@ -85,10 +85,10 @@ genX(compute_pipeline_create)(
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pipeline->use_repclear = false;
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anv_setup_pipeline_l3_config(pipeline);
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const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
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anv_pipeline_setup_l3_config(pipeline, cs_prog_data->base.total_shared > 0);
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uint32_t group_size = cs_prog_data->local_size[0] *
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cs_prog_data->local_size[1] * cs_prog_data->local_size[2];
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uint32_t remainder = group_size & (cs_prog_data->simd_size - 1);
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