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intel/fs: make tcs input_vertices dynamic

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We need to do 3 things to accomplish this :

   1. make all the register access consider the maximal case when
      unknown at compile time

   2. move the clamping of load_per_vertex_input prior to lowering
      nir_intrinsic_load_patch_vertices_in (in the dynamic cases, the
      clamping will use the nir_intrinsic_load_patch_vertices_in to
      clamp), meaning clamping using derefs rather than lowered
      nir_intrinsic_load_per_vertex_input

   3. in the known cases, lower nir_intrinsic_load_patch_vertices_in
      in NIR (so that the clamped elements still be vectorized to the
      smallest number of URB read messages)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22378>
This commit is contained in:
Lionel Landwerlin
2023-04-08 21:34:35 +03:00
committed by Marge Bot
parent 32b7659fff
commit 429ef02f83
7 changed files with 98 additions and 23 deletions
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8
src/intel/compiler/brw_nir.h
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@@ -98,6 +98,9 @@ struct brw_nir_compiler_opts {
/* Whether robust image access is enabled */
bool robust_image_access;
/* Input vertices for TCS stage (0 means dynamic) */
unsigned input_vertices;
};
void brw_preprocess_nir(const struct brw_compiler *compiler,
@@ -191,8 +194,9 @@ bool brw_nir_opt_peephole_ffma(nir_shader *shader);
bool brw_nir_opt_peephole_imul32x16(nir_shader *shader);
bool brw_nir_clamp_per_vertex_loads(nir_shader *shader,
unsigned input_vertices);
bool brw_nir_clamp_per_vertex_loads(nir_shader *shader);
bool brw_nir_lower_patch_vertices_in(nir_shader *shader, unsigned input_vertices);
bool brw_nir_blockify_uniform_loads(nir_shader *shader,
const struct intel_device_info *devinfo);