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radv: don't lower vectorized instructions to 32bit

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Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
This commit is contained in:
Daniel Schürmann
2022-06-27 14:49:49 +02:00
committed by Marge Bot
parent c298ab0d23
commit 4235dd7b47
1 changed files with 5 additions and 0 deletions
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5
src/amd/vulkan/radv_pipeline.c
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@@ -3990,6 +3990,11 @@ lower_bit_size_callback(const nir_instr *instr, void *_)
return 0; return 0;
nir_alu_instr *alu = nir_instr_as_alu(instr); nir_alu_instr *alu = nir_instr_as_alu(instr);
/* If an instruction is not scalarized by this point,
* it can be emitted as packed instruction */
if (alu->dest.dest.ssa.num_components > 1)
return 0;
if (alu->dest.dest.ssa.bit_size & (8 | 16)) { if (alu->dest.dest.ssa.bit_size & (8 | 16)) {
unsigned bit_size = alu->dest.dest.ssa.bit_size; unsigned bit_size = alu->dest.dest.ssa.bit_size;
switch (alu->op) { switch (alu->op) {