freedreno/ir3: Add ir3 intrinsics for tessellation
These provide the iovas for system memory buffers used for tessellation as well as a new HW specific system value. Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com> Acked-by: Eric Anholt <eric@anholt.net> Reviewed-by: Rob Clark <robdclark@gmail.com>
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@@ -792,6 +792,12 @@ system_value("vs_vertex_stride_ir3", 1)
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system_value("gs_header_ir3", 1)
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system_value("primitive_location_ir3", 1, indices=[DRIVER_LOCATION])
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# System values for freedreno tessellation shaders.
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system_value("hs_patch_stride_ir3", 1)
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system_value("tess_factor_base_ir3", 2)
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system_value("tess_param_base_ir3", 2)
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system_value("tcs_header_ir3", 1)
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# IR3-specific load/store intrinsics. These access a buffer used to pass data
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# between geometry stages - perhaps it's explicit access to the vertex cache.
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@@ -255,6 +255,7 @@ gl_system_value_name(gl_system_value sysval)
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ENUM(SYSTEM_VALUE_BARYCENTRIC_CENTROID),
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ENUM(SYSTEM_VALUE_BARYCENTRIC_SIZE),
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ENUM(SYSTEM_VALUE_GS_HEADER_IR3),
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ENUM(SYSTEM_VALUE_TCS_HEADER_IR3),
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};
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STATIC_ASSERT(ARRAY_SIZE(names) == SYSTEM_VALUE_MAX);
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return NAME(sysval);
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@@ -642,11 +642,12 @@ typedef enum
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SYSTEM_VALUE_BARYCENTRIC_SIZE,
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/**
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* IR3 specific geometry shader system value that packs invocation id,
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* thread id and vertex id. Having this as a nir level system value lets
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* us do the unpacking in nir.
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* IR3 specific geometry shader and tesselation control shader system
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* values that packs invocation id, thread id and vertex id. Having this
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* as a nir level system value lets us do the unpacking in nir.
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*/
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SYSTEM_VALUE_GS_HEADER_IR3,
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SYSTEM_VALUE_TCS_HEADER_IR3,
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SYSTEM_VALUE_MAX /**< Number of values */
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} gl_system_value;
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@@ -1363,6 +1363,21 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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case nir_intrinsic_load_vs_vertex_stride_ir3:
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dst[0] = create_uniform(b, primitive_param + 1);
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break;
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case nir_intrinsic_load_hs_patch_stride_ir3:
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dst[0] = create_uniform(b, primitive_param + 2);
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break;
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case nir_intrinsic_load_patch_vertices_in:
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dst[0] = create_uniform(b, primitive_param + 3);
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break;
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case nir_intrinsic_load_tess_param_base_ir3:
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dst[0] = create_uniform(b, primitive_param + 4);
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dst[1] = create_uniform(b, primitive_param + 5);
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break;
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case nir_intrinsic_load_tess_factor_base_ir3:
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dst[0] = create_uniform(b, primitive_param + 6);
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dst[1] = create_uniform(b, primitive_param + 7);
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break;
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case nir_intrinsic_load_primitive_location_ir3:
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idx = nir_intrinsic_driver_location(intr);
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dst[0] = create_uniform(b, primitive_map + idx);
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@@ -1371,6 +1386,9 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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case nir_intrinsic_load_gs_header_ir3:
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dst[0] = ctx->gs_header;
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break;
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case nir_intrinsic_load_tcs_header_ir3:
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dst[0] = ctx->tcs_header;
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break;
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case nir_intrinsic_load_primitive_id:
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dst[0] = ctx->primitive_id;
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@@ -80,6 +80,11 @@ struct ir3_context {
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struct ir3_instruction *primitive_id;
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struct ir3_instruction *gs_header;
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/* For tessellation shaders: */
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struct ir3_instruction *patch_vertices_in;
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struct ir3_instruction *tcs_header;
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struct ir3_instruction *tess_coord;
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/* Compute shader inputs: */
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struct ir3_instruction *local_invocation_id, *work_group_id;
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@@ -363,6 +363,8 @@ output_name(struct ir3_shader_variant *so, int i)
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return "GS_HEADER";
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case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
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return "GS_VERTEX_FLAGS";
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case VARYING_SLOT_TCS_HEADER_IR3:
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return "TCS_HEADER";
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default:
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return gl_varying_slot_name(so->outputs[i].slot);
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}
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@@ -738,6 +738,7 @@ ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
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#define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0)
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#define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1)
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#define VARYING_SLOT_TCS_HEADER_IR3 (VARYING_SLOT_MAX + 2)
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static inline uint32_t
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