freedreno/ir3: Add ir3 intrinsics for tessellation

These provide the iovas for system memory buffers used for
tessellation as well as a new HW specific system value.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Kristian H. Kristensen
2019-10-22 16:33:18 -07:00
parent d6209a50bb
commit 41984c8422
7 changed files with 37 additions and 3 deletions

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@@ -792,6 +792,12 @@ system_value("vs_vertex_stride_ir3", 1)
system_value("gs_header_ir3", 1) system_value("gs_header_ir3", 1)
system_value("primitive_location_ir3", 1, indices=[DRIVER_LOCATION]) system_value("primitive_location_ir3", 1, indices=[DRIVER_LOCATION])
# System values for freedreno tessellation shaders.
system_value("hs_patch_stride_ir3", 1)
system_value("tess_factor_base_ir3", 2)
system_value("tess_param_base_ir3", 2)
system_value("tcs_header_ir3", 1)
# IR3-specific load/store intrinsics. These access a buffer used to pass data # IR3-specific load/store intrinsics. These access a buffer used to pass data
# between geometry stages - perhaps it's explicit access to the vertex cache. # between geometry stages - perhaps it's explicit access to the vertex cache.

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@@ -255,6 +255,7 @@ gl_system_value_name(gl_system_value sysval)
ENUM(SYSTEM_VALUE_BARYCENTRIC_CENTROID), ENUM(SYSTEM_VALUE_BARYCENTRIC_CENTROID),
ENUM(SYSTEM_VALUE_BARYCENTRIC_SIZE), ENUM(SYSTEM_VALUE_BARYCENTRIC_SIZE),
ENUM(SYSTEM_VALUE_GS_HEADER_IR3), ENUM(SYSTEM_VALUE_GS_HEADER_IR3),
ENUM(SYSTEM_VALUE_TCS_HEADER_IR3),
}; };
STATIC_ASSERT(ARRAY_SIZE(names) == SYSTEM_VALUE_MAX); STATIC_ASSERT(ARRAY_SIZE(names) == SYSTEM_VALUE_MAX);
return NAME(sysval); return NAME(sysval);

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@@ -642,11 +642,12 @@ typedef enum
SYSTEM_VALUE_BARYCENTRIC_SIZE, SYSTEM_VALUE_BARYCENTRIC_SIZE,
/** /**
* IR3 specific geometry shader system value that packs invocation id, * IR3 specific geometry shader and tesselation control shader system
* thread id and vertex id. Having this as a nir level system value lets * values that packs invocation id, thread id and vertex id. Having this
* us do the unpacking in nir. * as a nir level system value lets us do the unpacking in nir.
*/ */
SYSTEM_VALUE_GS_HEADER_IR3, SYSTEM_VALUE_GS_HEADER_IR3,
SYSTEM_VALUE_TCS_HEADER_IR3,
SYSTEM_VALUE_MAX /**< Number of values */ SYSTEM_VALUE_MAX /**< Number of values */
} gl_system_value; } gl_system_value;

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@@ -1363,6 +1363,21 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
case nir_intrinsic_load_vs_vertex_stride_ir3: case nir_intrinsic_load_vs_vertex_stride_ir3:
dst[0] = create_uniform(b, primitive_param + 1); dst[0] = create_uniform(b, primitive_param + 1);
break; break;
case nir_intrinsic_load_hs_patch_stride_ir3:
dst[0] = create_uniform(b, primitive_param + 2);
break;
case nir_intrinsic_load_patch_vertices_in:
dst[0] = create_uniform(b, primitive_param + 3);
break;
case nir_intrinsic_load_tess_param_base_ir3:
dst[0] = create_uniform(b, primitive_param + 4);
dst[1] = create_uniform(b, primitive_param + 5);
break;
case nir_intrinsic_load_tess_factor_base_ir3:
dst[0] = create_uniform(b, primitive_param + 6);
dst[1] = create_uniform(b, primitive_param + 7);
break;
case nir_intrinsic_load_primitive_location_ir3: case nir_intrinsic_load_primitive_location_ir3:
idx = nir_intrinsic_driver_location(intr); idx = nir_intrinsic_driver_location(intr);
dst[0] = create_uniform(b, primitive_map + idx); dst[0] = create_uniform(b, primitive_map + idx);
@@ -1371,6 +1386,9 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
case nir_intrinsic_load_gs_header_ir3: case nir_intrinsic_load_gs_header_ir3:
dst[0] = ctx->gs_header; dst[0] = ctx->gs_header;
break; break;
case nir_intrinsic_load_tcs_header_ir3:
dst[0] = ctx->tcs_header;
break;
case nir_intrinsic_load_primitive_id: case nir_intrinsic_load_primitive_id:
dst[0] = ctx->primitive_id; dst[0] = ctx->primitive_id;

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@@ -80,6 +80,11 @@ struct ir3_context {
struct ir3_instruction *primitive_id; struct ir3_instruction *primitive_id;
struct ir3_instruction *gs_header; struct ir3_instruction *gs_header;
/* For tessellation shaders: */
struct ir3_instruction *patch_vertices_in;
struct ir3_instruction *tcs_header;
struct ir3_instruction *tess_coord;
/* Compute shader inputs: */ /* Compute shader inputs: */
struct ir3_instruction *local_invocation_id, *work_group_id; struct ir3_instruction *local_invocation_id, *work_group_id;

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@@ -363,6 +363,8 @@ output_name(struct ir3_shader_variant *so, int i)
return "GS_HEADER"; return "GS_HEADER";
case VARYING_SLOT_GS_VERTEX_FLAGS_IR3: case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
return "GS_VERTEX_FLAGS"; return "GS_VERTEX_FLAGS";
case VARYING_SLOT_TCS_HEADER_IR3:
return "TCS_HEADER";
default: default:
return gl_varying_slot_name(so->outputs[i].slot); return gl_varying_slot_name(so->outputs[i].slot);
} }

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@@ -738,6 +738,7 @@ ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
#define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0) #define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0)
#define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1) #define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1)
#define VARYING_SLOT_TCS_HEADER_IR3 (VARYING_SLOT_MAX + 2)
static inline uint32_t static inline uint32_t