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intel/eu: Set EXECUTE_1 when setting the rounding mode in cr0

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Fixes: d6cd14f213 "i965/fs: Define new shader opcode to..."
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
This commit is contained in:
Jason Ekstrand
2018-05-18 20:04:12 -07:00
parent fe2edb25dd
commit 417b9e5770
1 changed files with 2 additions and 0 deletions
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src/intel/compiler/brw_eu_emit.c
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@@ -3713,6 +3713,7 @@ brw_rounding_mode(struct brw_codegen *p,
if (bits != BRW_CR0_RND_MODE_MASK) { if (bits != BRW_CR0_RND_MODE_MASK) {
brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0), brw_inst *inst = brw_AND(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(~BRW_CR0_RND_MODE_MASK)); brw_imm_ud(~BRW_CR0_RND_MODE_MASK));
brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
/* From the Skylake PRM, Volume 7, page 760: /* From the Skylake PRM, Volume 7, page 760:
* "Implementation Restriction on Register Access: When the control * "Implementation Restriction on Register Access: When the control
@@ -3727,6 +3728,7 @@ brw_rounding_mode(struct brw_codegen *p,
if (bits) { if (bits) {
brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0), brw_inst *inst = brw_OR(p, brw_cr0_reg(0), brw_cr0_reg(0),
brw_imm_ud(bits)); brw_imm_ud(bits));
brw_inst_set_exec_size(p->devinfo, inst, BRW_EXECUTE_1);
brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH); brw_inst_set_thread_control(p->devinfo, inst, BRW_THREAD_SWITCH);
} }
} }