From 415c5ad9897bae5bfc1ad73cc08d7c5f734d96f0 Mon Sep 17 00:00:00 2001
From: Sagar Ghuge <sagar.ghuge@intel.com>
Date: Fri, 31 May 2024 10:12:35 -0700
Subject: [PATCH] intel/compiler: No need to re-type the destination register

For 16-bit float case handling, intermediate destination register is
already 32-bit wide, we don't have to retype it to 32-bit.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29506>
---
 src/intel/compiler/brw_fs_nir.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index b49e04ea7f8..ee1035e5dba 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -7713,8 +7713,7 @@ fs_nir_emit_surface_atomic(nir_to_brw_state &ntb, const fs_builder &bld,
          bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
                   retype(dest32, dest.type),
                   srcs, SURFACE_LOGICAL_NUM_SRCS);
-         bld.MOV(retype(dest, BRW_TYPE_UW),
-                 retype(dest32, BRW_TYPE_UD));
+         bld.MOV(retype(dest, BRW_TYPE_UW), dest32);
          break;
       }