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radv: add radv_shader_variant_get_va and radv_find_shader_variant helpers

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>
This commit is contained in:
Rhys Perry
2021-05-27 17:29:42 +01:00
committed by Marge Bot
parent d1f09419b4
commit 404752bfb2
7 changed files with 56 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/amd/vulkan/layers/radv_sqtt_layer.c
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@@ -884,7 +884,7 @@ radv_add_code_object(struct radv_device *device, struct radv_pipeline *pipeline)
}
memcpy(code, shader->code_ptr, shader->code_size);
va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
va = radv_shader_variant_get_va(shader);
record->shader_data[i].hash[0] = (uint64_t)(uintptr_t)shader;
record->shader_data[i].hash[1] = (uint64_t)(uintptr_t)shader >> 32;
@@ -929,7 +929,7 @@ radv_register_pipeline(struct radv_device *device, struct radv_pipeline *pipelin
if (!shader)
continue;
va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
va = radv_shader_variant_get_va(shader);
base_va = MIN2(base_va, va);
}

2
src/amd/vulkan/radv_cmd_buffer.c
View File

@@ -1061,7 +1061,7 @@ radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer, struct radv_shader
if (!shader)
return;
va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
va = radv_shader_variant_get_va(shader);
si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
}

38
src/amd/vulkan/radv_debug.c
View File

@@ -306,7 +306,7 @@ radv_dump_annotated_shader(struct radv_shader_variant *shader, gl_shader_stage s
if (!shader)
return;
start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
start_addr = radv_shader_variant_get_va(shader);
end_addr = start_addr + shader->code_size;
/* See if any wave executes the shader. */
@@ -883,38 +883,6 @@ radv_trap_handler_finish(struct radv_device *device)
}
}
static struct radv_shader_variant *
radv_get_faulty_shader(struct radv_device *device, uint64_t faulty_pc)
{
struct radv_shader_variant *shader = NULL;
mtx_lock(&device->shader_slab_mutex);
list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs)
{
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wshadow"
#endif
list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list)
{
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
uint64_t offset = align_u64(s->bo_offset + s->code_size, 256);
uint64_t va = radv_buffer_get_va(s->bo);
if (faulty_pc >= va + s->bo_offset && faulty_pc < va + offset) {
mtx_unlock(&device->shader_slab_mutex);
return s;
}
}
}
mtx_unlock(&device->shader_slab_mutex);
return shader;
}
static void
radv_dump_faulty_shader(struct radv_device *device, uint64_t faulty_pc)
{
@@ -922,11 +890,11 @@ radv_dump_faulty_shader(struct radv_device *device, uint64_t faulty_pc)
uint64_t start_addr, end_addr;
uint32_t instr_offset;
shader = radv_get_faulty_shader(device, faulty_pc);
shader = radv_find_shader_variant(device, faulty_pc);
if (!shader)
return;
start_addr = radv_buffer_get_va(shader->bo) + shader->bo_offset;
start_addr = radv_shader_variant_get_va(shader);
end_addr = start_addr + shader->code_size;
instr_offset = faulty_pc - start_addr;

16
src/amd/vulkan/radv_pipeline.c
View File

@@ -4385,7 +4385,7 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
const struct radv_pipeline *pipeline,
const struct radv_shader_variant *shader)
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
uint64_t va = radv_shader_variant_get_va(shader);
radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
radeon_emit(cs, va >> 8);
@@ -4458,7 +4458,7 @@ static void
radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs, const struct radv_pipeline *pipeline,
const struct radv_shader_variant *shader)
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
uint64_t va = radv_shader_variant_get_va(shader);
radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
radeon_emit(cs, va >> 8);
@@ -4472,7 +4472,7 @@ radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, const struct radv_pipelin
const struct radv_shader_variant *shader)
{
unsigned num_lds_blocks = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
uint64_t va = radv_shader_variant_get_va(shader);
uint32_t rsrc2 = shader->config.rsrc2;
radeon_set_sh_reg(cs, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
@@ -4492,7 +4492,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
const struct radv_pipeline *pipeline,
const struct radv_shader_variant *shader)
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
uint64_t va = radv_shader_variant_get_va(shader);
gl_shader_stage es_type =
radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
struct radv_shader_variant *es = es_type == MESA_SHADER_TESS_EVAL
@@ -4632,7 +4632,7 @@ static void
radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, const struct radv_pipeline *pipeline,
const struct radv_shader_variant *shader)
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
uint64_t va = radv_shader_variant_get_va(shader);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
@@ -4829,7 +4829,7 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
gs_state->vgt_esgs_ring_itemsize);
va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
va = radv_shader_variant_get_va(gs);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
@@ -5050,7 +5050,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct rade
assert(pipeline->shaders[MESA_SHADER_FRAGMENT]);
ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
va = radv_shader_variant_get_va(ps);
radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
radeon_emit(cs, va >> 8);
@@ -5620,7 +5620,7 @@ static void
radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs, const struct radv_pipeline *pipeline)
{
struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
uint64_t va = radv_shader_variant_get_va(shader);
struct radv_device *device = pipeline->device;
radeon_set_sh_reg(cs, R_00B830_COMPUTE_PGM_LO, va >> 8);

38
src/amd/vulkan/radv_shader.c
View File

@@ -1472,7 +1472,7 @@ radv_shader_variant_create(struct radv_device *device, const struct radv_shader_
struct radv_shader_binary_rtld *bin = (struct radv_shader_binary_rtld *)binary;
struct ac_rtld_upload_info info = {
.binary = &rtld_binary,
.rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
.rx_va = radv_shader_variant_get_va(variant),
.rx_ptr = dest_ptr,
};
@@ -1747,6 +1747,42 @@ radv_shader_variant_destroy(struct radv_device *device, struct radv_shader_varia
free(variant);
}
uint64_t
radv_shader_variant_get_va(const struct radv_shader_variant *variant)
{
return radv_buffer_get_va(variant->bo) + variant->bo_offset;
}
struct radv_shader_variant *
radv_find_shader_variant(struct radv_device *device, uint64_t pc)
{
mtx_lock(&device->shader_slab_mutex);
list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs)
{
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wshadow"
#endif
list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list)
{
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
uint64_t offset = align_u64(s->bo_offset + s->code_size, 256);
uint64_t va = radv_buffer_get_va(s->bo);
if (pc >= va + s->bo_offset && pc < va + offset) {
mtx_unlock(&device->shader_slab_mutex);
return s;
}
}
}
mtx_unlock(&device->shader_slab_mutex);
return NULL;
}
const char *
radv_get_shader_name(struct radv_shader_info *info, gl_shader_stage stage)
{

3
src/amd/vulkan/radv_shader.h
View File

@@ -458,6 +458,9 @@ struct radv_shader_variant *radv_create_trap_handler_shader(struct radv_device *
void radv_shader_variant_destroy(struct radv_device *device, struct radv_shader_variant *variant);
uint64_t radv_shader_variant_get_va(const struct radv_shader_variant *variant);
struct radv_shader_variant *radv_find_shader_variant(struct radv_device *device, uint64_t pc);
unsigned radv_get_max_waves(const struct radv_device *device, struct radv_shader_variant *variant,
gl_shader_stage stage);

6
src/amd/vulkan/si_cmd_buffer.c
View File

@@ -139,8 +139,7 @@ si_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs)
assert(device->physical_device->rad_info.chip_class == GFX8);
tba_va = radv_buffer_get_va(device->trap_handler_shader->bo) +
device->trap_handler_shader->bo_offset;
tba_va = radv_shader_variant_get_va(device->trap_handler_shader);
tma_va = radv_buffer_get_va(device->tma_bo);
radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4);
@@ -532,8 +531,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
assert(device->physical_device->rad_info.chip_class == GFX8);
tba_va = radv_buffer_get_va(device->trap_handler_shader->bo) +
device->trap_handler_shader->bo_offset;
tba_va = radv_shader_variant_get_va(device->trap_handler_shader);
tma_va = radv_buffer_get_va(device->tma_bo);
uint32_t regs[] = {R_00B000_SPI_SHADER_TBA_LO_PS, R_00B100_SPI_SHADER_TBA_LO_VS,