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intel/genxml: define MEMORYADDRESSATTRIBUTES for Gen12.5 with TILEF

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Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32775>
This commit is contained in:
Hyunjun Ko
2024-12-27 09:36:35 +09:00
committed by Marge Bot
parent 68477ae7c0
commit 3f3d6c04a3
1 changed files with 16 additions and 0 deletions
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16
src/intel/genxml/gen125.xml
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@@ -212,6 +212,22 @@
<field name="Rmin" start="192" end="223" type="uint" />
<field name="Aspect" start="224" end="255" type="uint" />
</struct>
<struct name="MEMORYADDRESSATTRIBUTES" length="1">
<field name="MOCS" start="0" end="6" type="uint" nonzero="true" />
<field name="Arbitration Priority Control" start="7" end="8" type="HEVC_ARBITRATION_PRIORITY" />
<field name="Memory Compression Enable" start="9" end="9" type="bool" />
<field name="Memory Compression Mode" start="10" end="10" type="uint" />
<field name="Row Store Scratch Buffer Cache Select" start="12" end="12" type="uint">
<value name="LLC" value="0" />
<value name="Internal Media Storage" value="1" />
</field>
<field name="Tiled Resource Mode" start="13" end="14" type="uint">
<value name="TRMODE_NONE" value="0" />
<value name="TRMODE_TILES" value="1" />
<value name="TRMODE_TILEX" value="2" />
<value name="TRMODE_TILEF" value="3" />
</field>
</struct>
<struct name="MI_MATH_ALU_INSTRUCTION" length="1">
<field name="Operand 2" start="0" end="9" type="uint" prefix="MI_ALU">
<value name="REG0" value="0x00" />