intel: Expose more FBconfigs in the 3D driver.

We can support any combination of (a8r8g8b8, x8r8g8b8, r5g6b5) x (z0,z24,z24s8)
on either class of chipsets.  The only restriction is no mixing bpp when also
mixing tiling.  This shouldn't be occurring currently.

src/mesa/drivers/dri/common/utils.h

@@ -133,7 +133,8 @@ driCreateConfigs(GLenum fb_format, GLenum fb_type,
 		 unsigned num_depth_stencil_bits,
 		 const GLenum * db_modes, unsigned num_db_modes);
 
-const __DRIconfig **driConcatConfigs(__DRIconfig **a, __DRIconfig **b);
+const __DRIconfig **driConcatConfigs(const __DRIconfig **a,
+				     const __DRIconfig **b);
 
 int
 driGetConfigAttrib(const __DRIconfig *config,