diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
index e5074162bcd..f6b78dff588 100644
--- a/include/drm-uapi/drm_fourcc.h
+++ b/include/drm-uapi/drm_fourcc.h
@@ -1341,6 +1341,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_TILE_VER_GFX9 1
 #define AMD_FMT_MOD_TILE_VER_GFX10 2
 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
+#define AMD_FMT_MOD_TILE_VER_GFX11 4
 
 /*
  * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
@@ -1356,6 +1357,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
+#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
 
 #define AMD_FMT_MOD_DCC_BLOCK_64B 0
 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 1035aba72b1..8e8ca14a794 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -218,6 +218,9 @@ bool ac_is_modifier_supported(const struct radeon_info *info,
    case GFX10_3:
       allowed_swizzles = ac_modifier_has_dcc(modifier) ? 0x08000000 : 0x0E660660;
       break;
+   case GFX11:
+      allowed_swizzles = ac_modifier_has_dcc(modifier) ? 0x88000000 : 0xCC440440;
+      break;
    default:
       return false;
    }
@@ -408,6 +411,71 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
       ADD_MOD(DRM_FORMAT_MOD_LINEAR)
       break;
    }
+   case GFX11: {
+      /* GFX11 has new microblock organization. No S modes for 2D. */
+      unsigned pipe_xor_bits = G_0098F8_NUM_PIPES(info->gb_addr_config);
+      unsigned pkrs = G_0098F8_NUM_PKRS(info->gb_addr_config);
+      unsigned num_pipes = 1 << pipe_xor_bits;
+
+      /* R_X swizzle modes are the best for rendering and DCC requires them. */
+      unsigned swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X :
+                                              AMD_FMT_MOD_TILE_GFX9_64K_R_X;
+      uint64_t modifier_r_x = AMD_FMT_MOD |
+                              AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
+                              AMD_FMT_MOD_SET(TILE, swizzle_r_x) |
+                              AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+                              AMD_FMT_MOD_SET(PACKERS, pkrs);
+
+      /* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */
+      uint64_t modifier_dcc_best = modifier_r_x |
+                                   AMD_FMT_MOD_SET(DCC, 1) |
+                                   AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) |
+                                   AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+                                   AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
+
+      /* DCC settings for 4K and greater resolutions. (required by display hw) */
+      uint64_t modifier_dcc_4k = modifier_r_x |
+                                 AMD_FMT_MOD_SET(DCC, 1) |
+                                 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+                                 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+                                 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
+
+      /* Modifiers have to be sorted from best to worst.
+       *
+       * Top level order:
+       *   1. The best chip-specific modifiers with DCC, potentially non-displayable.
+       *   2. Chip-specific displayable modifiers with DCC.
+       *   3. Chip-specific displayable modifiers without DCC.
+       *   4. Chip-independent modifiers without DCC.
+       *   5. Linear.
+       */
+
+      /* Add the best non-displayable modifier first. */
+      ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1));
+
+      /* Displayable modifiers are next. */
+      /* These two will only be used by chips with 1 RB, and they are the best choice there. */
+      if (info->max_render_backends == 1) {
+         ADD_MOD(modifier_dcc_best)
+         ADD_MOD(modifier_dcc_4k)
+      }
+
+      /* Add other displayable DCC settings. (DCC_RETILE implies displayable on all chips) */
+      ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1))
+      ADD_MOD(modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1))
+
+      /* Add one without DCC that is displayable (it's also optimal for non-displayable cases). */
+      ADD_MOD(modifier_r_x)
+
+      /* Add one that is compatible with other gfx11 chips. */
+      ADD_MOD(AMD_FMT_MOD |
+              AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
+              AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D))
+
+      /* Linear must be last. */
+      ADD_MOD(DRM_FORMAT_MOD_LINEAR)
+      break;
+   }
    default:
       break;
    }