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radv: Allow using high 16 bits of PS input slots.

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Add a new float16_hi_shaded_mask to keep track of which PS input
slots use their high 16 bits, based on the high_16bits of the
NIR IO semantics. Then, set ATTR1_VALID accordingly.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28764>
This commit is contained in:
Timur Kristóf
2024-04-16 14:50:05 +02:00
committed by Marge Bot
parent 12c0c20ed1
commit 3dd758f72c
3 changed files with 12 additions and 1 deletions
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7
src/amd/vulkan/radv_pipeline_graphics.c
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@@ -3346,6 +3346,7 @@ enum radv_ps_in_type {
radv_ps_in_explicit, radv_ps_in_explicit,
radv_ps_in_explicit_strict, radv_ps_in_explicit_strict,
radv_ps_in_interpolated_fp16, radv_ps_in_interpolated_fp16,
radv_ps_in_interpolated_fp16_hi,
radv_ps_in_per_prim_gfx103, radv_ps_in_per_prim_gfx103,
radv_ps_in_per_prim_gfx11, radv_ps_in_per_prim_gfx11,
}; };
@@ -3375,7 +3376,11 @@ offset_to_ps_input(const uint32_t offset, const enum radv_ps_in_type type)
case radv_ps_in_flat: case radv_ps_in_flat:
ps_input_cntl |= S_028644_FLAT_SHADE(1); ps_input_cntl |= S_028644_FLAT_SHADE(1);
break; break;
case radv_ps_in_interpolated_fp16_hi:
ps_input_cntl |= S_028644_ATTR1_VALID(1);
FALLTHROUGH;
case radv_ps_in_interpolated_fp16: case radv_ps_in_interpolated_fp16:
/* These must be set even if only the high 16 bits are used. */
ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) | S_028644_ATTR0_VALID(1); ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) | S_028644_ATTR0_VALID(1);
break; break;
case radv_ps_in_per_prim_gfx11: case radv_ps_in_per_prim_gfx11:
@@ -3426,6 +3431,8 @@ input_mask_to_ps_inputs(const struct radv_vs_output_info *outinfo, const struct
type = radv_ps_in_explicit; type = radv_ps_in_explicit;
else if (ps->info.ps.per_vertex_shaded_mask & BITFIELD_BIT(*ps_offset)) else if (ps->info.ps.per_vertex_shaded_mask & BITFIELD_BIT(*ps_offset))
type = radv_ps_in_explicit_strict; type = radv_ps_in_explicit_strict;
else if (ps->info.ps.float16_hi_shaded_mask & BITFIELD_BIT(*ps_offset))
type = radv_ps_in_interpolated_fp16_hi;
else if (ps->info.ps.float16_shaded_mask & BITFIELD_BIT(*ps_offset)) else if (ps->info.ps.float16_shaded_mask & BITFIELD_BIT(*ps_offset))
type = radv_ps_in_interpolated_fp16; type = radv_ps_in_interpolated_fp16;

5
src/amd/vulkan/radv_shader_info.c
View File

@@ -96,7 +96,10 @@ gather_load_fs_input_info(const nir_shader *nir, const nir_intrinsic_instr *intr
else else
info->ps.explicit_shaded_mask |= mapped_mask; info->ps.explicit_shaded_mask |= mapped_mask;
} else if (intrin->intrinsic == nir_intrinsic_load_interpolated_input && intrin->def.bit_size == 16) { } else if (intrin->intrinsic == nir_intrinsic_load_interpolated_input && intrin->def.bit_size == 16) {
info->ps.float16_shaded_mask |= mapped_mask; if (io_sem.high_16bits)
info->ps.float16_hi_shaded_mask |= mapped_mask;
else
info->ps.float16_shaded_mask |= mapped_mask;
} }
} }

1
src/amd/vulkan/radv_shader_info.h
View File

@@ -175,6 +175,7 @@ struct radv_shader_info {
uint32_t explicit_shaded_mask; uint32_t explicit_shaded_mask;
uint32_t per_vertex_shaded_mask; uint32_t per_vertex_shaded_mask;
uint32_t float16_shaded_mask; uint32_t float16_shaded_mask;
uint32_t float16_hi_shaded_mask;
uint32_t num_interp; uint32_t num_interp;
uint32_t num_prim_interp; uint32_t num_prim_interp;
bool can_discard; bool can_discard;