From 3dd758f72c5ff7d2e48c2b7adbb0e0411b90cf4c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Tue, 16 Apr 2024 14:50:05 +0200 Subject: [PATCH] radv: Allow using high 16 bits of PS input slots. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new float16_hi_shaded_mask to keep track of which PS input slots use their high 16 bits, based on the high_16bits of the NIR IO semantics. Then, set ATTR1_VALID accordingly. Signed-off-by: Timur Kristóf Reviewed-by: Georg Lehmann Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_pipeline_graphics.c | 7 +++++++ src/amd/vulkan/radv_shader_info.c | 5 ++++- src/amd/vulkan/radv_shader_info.h | 1 + 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 3cd9a0e3c41..35e05777288 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -3346,6 +3346,7 @@ enum radv_ps_in_type { radv_ps_in_explicit, radv_ps_in_explicit_strict, radv_ps_in_interpolated_fp16, + radv_ps_in_interpolated_fp16_hi, radv_ps_in_per_prim_gfx103, radv_ps_in_per_prim_gfx11, }; @@ -3375,7 +3376,11 @@ offset_to_ps_input(const uint32_t offset, const enum radv_ps_in_type type) case radv_ps_in_flat: ps_input_cntl |= S_028644_FLAT_SHADE(1); break; + case radv_ps_in_interpolated_fp16_hi: + ps_input_cntl |= S_028644_ATTR1_VALID(1); + FALLTHROUGH; case radv_ps_in_interpolated_fp16: + /* These must be set even if only the high 16 bits are used. */ ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) | S_028644_ATTR0_VALID(1); break; case radv_ps_in_per_prim_gfx11: @@ -3426,6 +3431,8 @@ input_mask_to_ps_inputs(const struct radv_vs_output_info *outinfo, const struct type = radv_ps_in_explicit; else if (ps->info.ps.per_vertex_shaded_mask & BITFIELD_BIT(*ps_offset)) type = radv_ps_in_explicit_strict; + else if (ps->info.ps.float16_hi_shaded_mask & BITFIELD_BIT(*ps_offset)) + type = radv_ps_in_interpolated_fp16_hi; else if (ps->info.ps.float16_shaded_mask & BITFIELD_BIT(*ps_offset)) type = radv_ps_in_interpolated_fp16; diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 5026c519f26..00bda50aabf 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -96,7 +96,10 @@ gather_load_fs_input_info(const nir_shader *nir, const nir_intrinsic_instr *intr else info->ps.explicit_shaded_mask |= mapped_mask; } else if (intrin->intrinsic == nir_intrinsic_load_interpolated_input && intrin->def.bit_size == 16) { - info->ps.float16_shaded_mask |= mapped_mask; + if (io_sem.high_16bits) + info->ps.float16_hi_shaded_mask |= mapped_mask; + else + info->ps.float16_shaded_mask |= mapped_mask; } } diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h index bd3b17f5aaf..a74822b4983 100644 --- a/src/amd/vulkan/radv_shader_info.h +++ b/src/amd/vulkan/radv_shader_info.h @@ -175,6 +175,7 @@ struct radv_shader_info { uint32_t explicit_shaded_mask; uint32_t per_vertex_shaded_mask; uint32_t float16_shaded_mask; + uint32_t float16_hi_shaded_mask; uint32_t num_interp; uint32_t num_prim_interp; bool can_discard;