diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index f1e6fadd285..ecc1c39f3cc 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2582,7 +2582,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
                                     .layerCount = 1,
                                  },
                            },
-                           NULL);
+                           0, NULL);
 
       radv_initialise_vrs_surface(image, htile_buffer, &ds);
 
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 8aa7f4933dd..499262531b8 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -952,7 +952,8 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
                               const VkComponentMapping *mapping, unsigned first_level,
                               unsigned last_level, unsigned first_layer, unsigned last_layer,
                               unsigned width, unsigned height, unsigned depth, float min_lod,
-                              uint32_t *state, uint32_t *fmask_state)
+                              uint32_t *state, uint32_t *fmask_state,
+                              VkImageCreateFlags img_create_flags)
 {
    const struct util_format_description *desc;
    enum pipe_swizzle swizzle[4];
@@ -976,8 +977,14 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
 
    radv_compose_swizzle(desc, mapping, swizzle);
 
-   type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
-                       is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
+   if (img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) {
+      assert(image->type == VK_IMAGE_TYPE_3D);
+      type = V_008F1C_SQ_RSRC_IMG_3D;
+   } else {
+      type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
+                          is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
+   }
+
    if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
       height = 1;
       depth = image->info.array_size;
@@ -1013,6 +1020,18 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
    state[6] = 0;
    state[7] = 0;
 
+   if (img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) {
+      assert(type == V_008F1C_SQ_RSRC_IMG_3D);
+
+      /* ARRAY_PITCH is only meaningful for 3D images, 0 means SRV, 1 means UAV.
+       * In SRV mode, BASE_ARRAY is ignored and DEPTH is the last slice of mipmap level 0.
+       * In UAV mode, BASE_ARRAY is the first slice and DEPTH is the last slice of the bound level.
+       */
+      state[4] &= C_00A010_DEPTH;
+      state[4] |= S_00A010_DEPTH(!is_storage_image ? depth - 1 : u_minify(depth, first_level) - 1);
+      state[5] |= S_00A014_ARRAY_PITCH(is_storage_image);
+   }
+
    if (radv_dcc_enabled(image, first_level)) {
       state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
                   S_00A018_MAX_COMPRESSED_BLOCK_SIZE(
@@ -1086,7 +1105,8 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
                            const VkComponentMapping *mapping, unsigned first_level,
                            unsigned last_level, unsigned first_layer, unsigned last_layer,
                            unsigned width, unsigned height, unsigned depth, float min_lod,
-                           uint32_t *state, uint32_t *fmask_state)
+                           uint32_t *state, uint32_t *fmask_state,
+                           VkImageCreateFlags img_create_flags)
 {
    const struct util_format_description *desc;
    enum pipe_swizzle swizzle[4];
@@ -1128,8 +1148,16 @@ si_make_texture_descriptor(struct radv_device *device, struct radv_image *image,
       else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
          data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
    }
-   type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
-                       is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
+
+   if (device->physical_device->rad_info.chip_class == GFX9 &&
+       img_create_flags & VK_IMAGE_CREATE_2D_VIEW_COMPATIBLE_BIT_EXT) {
+      assert(image->type == VK_IMAGE_TYPE_3D);
+      type = V_008F1C_SQ_RSRC_IMG_3D;
+   } else {
+      type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
+                          is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
+   }
+
    if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
       height = 1;
       depth = image->info.array_size;
@@ -1291,16 +1319,16 @@ radv_make_texture_descriptor(struct radv_device *device, struct radv_image *imag
                              const VkComponentMapping *mapping, unsigned first_level,
                              unsigned last_level, unsigned first_layer, unsigned last_layer,
                              unsigned width, unsigned height, unsigned depth, float min_lod, uint32_t *state,
-                             uint32_t *fmask_state)
+                             uint32_t *fmask_state, VkImageCreateFlags img_create_flags)
 {
    if (device->physical_device->rad_info.chip_class >= GFX10) {
       gfx10_make_texture_descriptor(device, image, is_storage_image, view_type, vk_format, mapping,
                                     first_level, last_level, first_layer, last_layer, width, height,
-                                    depth, min_lod, state, fmask_state);
+                                    depth, min_lod, state, fmask_state, img_create_flags);
    } else {
       si_make_texture_descriptor(device, image, is_storage_image, view_type, vk_format, mapping,
                                  first_level, last_level, first_layer, last_layer, width, height,
-                                 depth, min_lod, state, fmask_state);
+                                 depth, min_lod, state, fmask_state, img_create_flags);
    }
 }
 
@@ -1316,7 +1344,7 @@ radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image,
    radv_make_texture_descriptor(device, image, false, (VkImageViewType)image->type,
                                 image->vk_format, &fixedmapping, 0, image->info.levels - 1, 0,
                                 image->info.array_size - 1, image->info.width, image->info.height,
-                                image->info.depth, 0.0f, desc, NULL);
+                                image->info.depth, 0.0f, desc, NULL, 0);
 
    si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0,
                                   0, image->planes[0].surface.blk_w, false, false, false, false,
@@ -1899,7 +1927,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
                                 float min_lod,
                                 bool is_storage_image, bool disable_compression,
                                 bool enable_compression, unsigned plane_id,
-                                unsigned descriptor_plane_id)
+                                unsigned descriptor_plane_id, VkImageCreateFlags img_create_flags)
 {
    struct radv_image *image = iview->image;
    struct radv_image_plane *plane = &image->planes[plane_id];
@@ -1928,7 +1956,8 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
       vk_format_get_plane_width(image->vk_format, plane_id, iview->extent.width),
       vk_format_get_plane_height(image->vk_format, plane_id, iview->extent.height),
       iview->extent.depth, min_lod, descriptor->plane_descriptors[descriptor_plane_id],
-      descriptor_plane_id || is_storage_image ? NULL : descriptor->fmask_descriptor);
+      descriptor_plane_id || is_storage_image ? NULL : descriptor->fmask_descriptor,
+      img_create_flags);
 
    const struct legacy_surf_level *base_level_info = NULL;
    if (device->physical_device->rad_info.chip_class <= GFX9) {
@@ -2016,6 +2045,7 @@ radv_image_view_can_fast_clear(const struct radv_device *device,
 void
 radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
                      const VkImageViewCreateInfo *pCreateInfo,
+                     VkImageCreateFlags img_create_flags,
                      const struct radv_image_view_extra_create_info *extra_create_info)
 {
    RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
@@ -2172,10 +2202,10 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
       VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
       radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, min_lod, false,
                                       disable_compression, enable_compression, iview->plane_id + i,
-                                      i);
+                                      i, img_create_flags);
       radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, min_lod, true,
                                       disable_compression, enable_compression, iview->plane_id + i,
-                                      i);
+                                      i, img_create_flags);
    }
 }
 
@@ -2432,6 +2462,7 @@ VKAPI_ATTR VkResult VKAPI_CALL
 radv_CreateImageView(VkDevice _device, const VkImageViewCreateInfo *pCreateInfo,
                      const VkAllocationCallbacks *pAllocator, VkImageView *pView)
 {
+   RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
    RADV_FROM_HANDLE(radv_device, device, _device);
    struct radv_image_view *view;
 
@@ -2440,7 +2471,7 @@ radv_CreateImageView(VkDevice _device, const VkImageViewCreateInfo *pCreateInfo,
    if (view == NULL)
       return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
 
-   radv_image_view_init(view, device, pCreateInfo, NULL);
+   radv_image_view_init(view, device, pCreateInfo, image->flags, NULL);
 
    *pView = radv_image_view_to_handle(view);
 
diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index 2d7ab1e473c..258ec8ce639 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -579,7 +579,7 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
                                                    .baseArrayLayer = dst_array_slice,
                                                    .layerCount = 1},
                            },
-                           NULL);
+                           0, NULL);
       radv_image_view_init(&src_iview, cmd_buffer->device,
                            &(VkImageViewCreateInfo){
                               .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
@@ -592,7 +592,7 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
                                                    .baseArrayLayer = src_array_slice,
                                                    .layerCount = 1},
                            },
-                           NULL);
+                           0, NULL);
       meta_emit_blit(cmd_buffer, src_image, &src_iview, src_image_layout, src_offset_0,
                      src_offset_1, dst_image, &dst_iview, dst_image_layout, dst_offset_0,
                      dst_offset_1, dst_box, sampler);
diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c
index 134f7bef206..ac2cb4558fb 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -70,7 +70,7 @@ create_iview(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *s
                                                 .baseArrayLayer = surf->layer,
                                                 .layerCount = 1},
                         },
-                        &(struct radv_image_view_extra_create_info){
+                        0, &(struct radv_image_view_extra_create_info){
                            .disable_dcc_mrt = surf->disable_compression
                         });
 }
diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c
index e544dea2a1e..594ddc17b80 100644
--- a/src/amd/vulkan/radv_meta_bufimage.c
+++ b/src/amd/vulkan/radv_meta_bufimage.c
@@ -1237,7 +1237,7 @@ create_iview(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *s
                                                 .baseArrayLayer = surf->layer,
                                                 .layerCount = 1},
                         },
-                        &(struct radv_image_view_extra_create_info){
+                        0, &(struct radv_image_view_extra_create_info){
                            .disable_compression = surf->disable_compression,
                         });
 }
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 4c97c1fb7fc..c61c4862c44 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1414,7 +1414,7 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer,
                                  .baseArrayLayer = range->baseArrayLayer,
                                  .layerCount = layer_count},
          },
-         &(struct radv_image_view_extra_create_info){.disable_compression = true});
+         0, &(struct radv_image_view_extra_create_info){.disable_compression = true});
 
       radv_meta_push_descriptor_set(
          cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
@@ -1973,7 +1973,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *im
                                                 .baseArrayLayer = range->baseArrayLayer,
                                                 .layerCount = layer_count},
                         },
-                        NULL);
+                        0, NULL);
 
    VkClearAttachment clear_att = {
       .aspectMask = range->aspectMask,
@@ -2071,7 +2071,7 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
                                  .layerCount = range->layerCount,
                               },
                         },
-                        NULL);
+                        0, NULL);
 
    VkClearRect clear_rect = {
       .rect =
diff --git a/src/amd/vulkan/radv_meta_copy_vrs_htile.c b/src/amd/vulkan/radv_meta_copy_vrs_htile.c
index d4b87939fe5..a5cfbc2e37e 100644
--- a/src/amd/vulkan/radv_meta_copy_vrs_htile.c
+++ b/src/amd/vulkan/radv_meta_copy_vrs_htile.c
@@ -252,7 +252,7 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i
                                                 .baseArrayLayer = 0,
                                                 .layerCount = 1},
                         },
-                        NULL);
+                        0, NULL);
 
    radv_meta_push_descriptor_set(
       cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, state->copy_vrs_htile_p_layout, 0, /* set */
diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c
index bc811828608..4b7fea1d074 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -429,7 +429,7 @@ radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i
                                  .layerCount = 1,
                               },
                         },
-                        NULL);
+                        0, NULL);
 
    const VkRenderingAttachmentInfo depth_att = {
       .sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
@@ -576,7 +576,7 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad
                                     .baseArrayLayer = subresourceRange->baseArrayLayer + s,
                                     .layerCount = 1},
             },
-            &(struct radv_image_view_extra_create_info){.enable_compression = true});
+            0, &(struct radv_image_view_extra_create_info){.enable_compression = true});
          radv_image_view_init(
             &store_iview, cmd_buffer->device,
             &(VkImageViewCreateInfo){
@@ -590,7 +590,7 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad
                                     .baseArrayLayer = subresourceRange->baseArrayLayer + s,
                                     .layerCount = 1},
             },
-            &(struct radv_image_view_extra_create_info){.disable_compression = true});
+            0, &(struct radv_image_view_extra_create_info){.disable_compression = true});
 
          radv_meta_push_descriptor_set(
             cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
diff --git a/src/amd/vulkan/radv_meta_etc_decode.c b/src/amd/vulkan/radv_meta_etc_decode.c
index 4920d8a209b..f8d80139717 100644
--- a/src/amd/vulkan/radv_meta_etc_decode.c
+++ b/src/amd/vulkan/radv_meta_etc_decode.c
@@ -753,7 +753,7 @@ radv_meta_decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
                .layerCount = subresource->baseArrayLayer + subresource->layerCount,
             },
       },
-      NULL);
+      0, NULL);
 
    VkFormat store_format;
    switch (image->vk_format) {
@@ -789,7 +789,7 @@ radv_meta_decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
                .layerCount = subresource->baseArrayLayer + subresource->layerCount,
             },
       },
-      NULL);
+      0, NULL);
 
    decode_etc(cmd_buffer, &src_iview, &dest_iview, &(VkOffset3D){offset.x, offset.y, base_slice},
               &(VkExtent3D){extent.width, extent.height, slice_count});
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index bc6b0aa6bf3..43ef3ba7f1d 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -504,7 +504,7 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i
                                  .layerCount = 1,
                               },
                         },
-                        NULL);
+                        0, NULL);
 
    const VkRenderingAttachmentInfo color_att = {
       .sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
@@ -765,7 +765,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
                                     .baseArrayLayer = subresourceRange->baseArrayLayer + s,
                                     .layerCount = 1},
             },
-            &(struct radv_image_view_extra_create_info){.enable_compression = true});
+            0, &(struct radv_image_view_extra_create_info){.enable_compression = true});
          radv_image_view_init(
             &store_iview, cmd_buffer->device,
             &(VkImageViewCreateInfo){
@@ -779,7 +779,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
                                     .baseArrayLayer = subresourceRange->baseArrayLayer + s,
                                     .layerCount = 1},
             },
-            &(struct radv_image_view_extra_create_info){.disable_compression = true});
+            0, &(struct radv_image_view_extra_create_info){.disable_compression = true});
 
          radv_meta_push_descriptor_set(
             cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
diff --git a/src/amd/vulkan/radv_meta_fmask_copy.c b/src/amd/vulkan/radv_meta_fmask_copy.c
index bcfdc01eb27..38855f1267a 100644
--- a/src/amd/vulkan/radv_meta_fmask_copy.c
+++ b/src/amd/vulkan/radv_meta_fmask_copy.c
@@ -314,7 +314,7 @@ radv_fmask_copy(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf
                                  .layerCount = 1,
                               },
                         },
-                        NULL);
+                        0, NULL);
 
    radv_image_view_init(&dst_iview, device,
                         &(VkImageViewCreateInfo){
@@ -331,7 +331,7 @@ radv_fmask_copy(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf
                                  .layerCount = 1,
                               },
                         },
-                        NULL);
+                        0, NULL);
 
    radv_meta_push_descriptor_set(
       cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
diff --git a/src/amd/vulkan/radv_meta_fmask_expand.c b/src/amd/vulkan/radv_meta_fmask_expand.c
index 4a1f126315a..577044b9734 100644
--- a/src/amd/vulkan/radv_meta_fmask_expand.c
+++ b/src/amd/vulkan/radv_meta_fmask_expand.c
@@ -124,7 +124,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_
                                  .layerCount = layer_count,
                               },
                         },
-                        NULL);
+                        0, NULL);
 
    radv_meta_push_descriptor_set(
       cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index e9dc15b014b..9db6c08da91 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -446,7 +446,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
                                     .layerCount = 1,
                                  },
                            },
-                           NULL);
+                           0, NULL);
 
       struct radv_image_view dst_iview;
       radv_image_view_init(&dst_iview, cmd_buffer->device,
@@ -464,7 +464,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
                                     .layerCount = 1,
                                  },
                            },
-                           NULL);
+                           0, NULL);
 
       const VkRenderingAttachmentInfo color_atts[2] = {
          {
diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c
index aa14b910e95..eda2e19dd14 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -724,7 +724,7 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_
                                     .layerCount = 1,
                                  },
                            },
-                           NULL);
+                           0, NULL);
 
       struct radv_image_view dest_iview;
       radv_image_view_init(&dest_iview, cmd_buffer->device,
@@ -742,7 +742,7 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_
                                     .layerCount = 1,
                                  },
                            },
-                           NULL);
+                           0, NULL);
 
       emit_resolve(cmd_buffer, &src_iview, &dest_iview, &(VkOffset2D){srcOffset.x, srcOffset.y},
                    &(VkOffset2D){dstOffset.x, dstOffset.y},
@@ -892,7 +892,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
                                  .layerCount = layer_count,
                               },
                         },
-                        NULL);
+                        0, NULL);
 
    struct radv_image_view tdst_iview;
    radv_image_view_init(&tdst_iview, cmd_buffer->device,
@@ -910,7 +910,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
                                  .layerCount = layer_count,
                               },
                         },
-                        NULL);
+                        0, NULL);
 
    emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, &tdst_iview,
                               &(VkExtent3D){fb->width, fb->height, layer_count}, aspects,
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c
index 074cbecdc7a..e5897a08cde 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -839,7 +839,7 @@ radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv
                                     .layerCount = 1,
                                  },
                            },
-                           NULL);
+                           0, NULL);
 
       struct radv_image_view dest_iview;
       radv_image_view_init(&dest_iview, cmd_buffer->device,
@@ -857,7 +857,7 @@ radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv
                                     .layerCount = 1,
                                  },
                            },
-                           NULL);
+                           0, NULL);
 
       const VkRenderingAttachmentInfo color_att = {
          .sType = VK_STRUCTURE_TYPE_RENDERING_ATTACHMENT_INFO,
@@ -1007,7 +1007,7 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
                                  .layerCount = 1,
                               },
                         },
-                        NULL);
+                        0, NULL);
 
    emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, dst_iview,
                               &(VkExtent2D){fb->width, fb->height}, aspects, resolve_mode);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 53b5a5dd5ba..6df9f16c75d 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -2509,6 +2509,7 @@ struct radv_image_view_extra_create_info {
 
 void radv_image_view_init(struct radv_image_view *view, struct radv_device *device,
                           const VkImageViewCreateInfo *pCreateInfo,
+                          VkImageCreateFlags img_create_flags,
                           const struct radv_image_view_extra_create_info *extra_create_info);
 void radv_image_view_finish(struct radv_image_view *iview);