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nir: split nir_lower_mov64

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ACO will want to lower the conversions, but preserve the bcsels.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23926>
This commit is contained in:
Rhys Perry
2023-06-27 19:19:39 +01:00
committed by Marge Bot
parent bd43d9e3d9
commit 3d0e997e99
3 changed files with 7 additions and 4 deletions
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3
src/compiler/nir/nir.h
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@@ -3425,7 +3425,7 @@ typedef enum {
nir_lower_divmod64 = (1 << 2), nir_lower_divmod64 = (1 << 2),
/** Lower all 64-bit umul_high and imul_high opcodes */ /** Lower all 64-bit umul_high and imul_high opcodes */
nir_lower_imul_high64 = (1 << 3), nir_lower_imul_high64 = (1 << 3),
nir_lower_mov64 = (1 << 4), nir_lower_bcsel64 = (1 << 4),
nir_lower_icmp64 = (1 << 5), nir_lower_icmp64 = (1 << 5),
nir_lower_iadd64 = (1 << 6), nir_lower_iadd64 = (1 << 6),
nir_lower_iabs64 = (1 << 7), nir_lower_iabs64 = (1 << 7),
@@ -3444,6 +3444,7 @@ typedef enum {
nir_lower_usub_sat64 = (1 << 20), nir_lower_usub_sat64 = (1 << 20),
nir_lower_iadd_sat64 = (1 << 21), nir_lower_iadd_sat64 = (1 << 21),
nir_lower_find_lsb64 = (1 << 22), nir_lower_find_lsb64 = (1 << 22),
nir_lower_conv64 = (1 << 23),
} nir_lower_int64_options; } nir_lower_int64_options;
typedef enum { typedef enum {

3
src/compiler/nir/nir_lower_int64.c
View File

@@ -909,8 +909,9 @@ nir_lower_int64_op_to_options_mask(nir_op opcode)
case nir_op_u2f16: case nir_op_u2f16:
case nir_op_f2i64: case nir_op_f2i64:
case nir_op_f2u64: case nir_op_f2u64:
return nir_lower_conv64;
case nir_op_bcsel: case nir_op_bcsel:
return nir_lower_mov64; return nir_lower_bcsel64;
case nir_op_ieq: case nir_op_ieq:
case nir_op_ine: case nir_op_ine:
case nir_op_ult: case nir_op_ult:

5
src/nouveau/codegen/nv50_ir_from_nir.cpp
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@@ -3405,7 +3405,7 @@ nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_isign64 : 0) | ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_isign64 : 0) |
nir_lower_divmod64 | nir_lower_divmod64 |
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_high64 : 0) | ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_high64 : 0) |
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_mov64 : 0) | ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_bcsel64 : 0) |
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_icmp64 : 0) | ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_icmp64 : 0) |
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_iabs64 : 0) | ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_iabs64 : 0) |
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_ineg64 : 0) | ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_ineg64 : 0) |
@@ -3414,7 +3414,8 @@ nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_shift64 : 0) | ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_shift64 : 0) |
nir_lower_imul_2x32_64 | nir_lower_imul_2x32_64 |
((chipset >= NVISA_GM107_CHIPSET) ? nir_lower_extract64 : 0) | ((chipset >= NVISA_GM107_CHIPSET) ? nir_lower_extract64 : 0) |
nir_lower_ufind_msb64 nir_lower_ufind_msb64 |
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_conv64 : 0)
); );
op.lower_doubles_options = (nir_lower_doubles_options) ( op.lower_doubles_options = (nir_lower_doubles_options) (
((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_drcp : 0) | ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_drcp : 0) |