intel/vec4: Make implied_mrf_writes() a vec4_instruction method

Same as commit c20dc9b836 (intel/fs: Make implied_mrf_writes() an
fs_inst method.)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>

src/intel/compiler/brw_ir_vec4.h

@@ -295,6 +295,7 @@ public:
    bool can_do_writemask(const struct gen_device_info *devinfo);
    bool can_change_types() const;
    bool has_source_and_destination_hazard() const;
+   unsigned implied_mrf_writes() const;
 
    bool is_align1_partial_write()
    {

src/intel/compiler/brw_schedule_instructions.cpp

@@ -1418,7 +1418,7 @@ vec4_instruction_scheduler::calculate_deps()
       }
 
       if (inst->mlen > 0 && !inst->is_send_from_grf()) {
-         for (int i = 0; i < v->implied_mrf_writes(inst); i++) {
+         for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
             add_dep(last_mrf_write[inst->base_mrf + i], n);
             last_mrf_write[inst->base_mrf + i] = n;
          }
@@ -1495,7 +1495,7 @@ vec4_instruction_scheduler::calculate_deps()
       }
 
       if (inst->mlen > 0 && !inst->is_send_from_grf()) {
-         for (int i = 0; i < v->implied_mrf_writes(inst); i++) {
+         for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
             last_mrf_write[inst->base_mrf + i] = n;
          }
       }

src/intel/compiler/brw_vec4.cpp

@@ -326,13 +326,13 @@ vec4_instruction::can_change_types() const
  * instruction -- the generate_* functions generate additional MOVs
  * for setup.
  */
-int
-vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
+unsigned
+vec4_instruction::implied_mrf_writes() const
 {
-   if (inst->mlen == 0 || inst->is_send_from_grf())
+   if (mlen == 0 || is_send_from_grf())
       return 0;
 
-   switch (inst->opcode) {
+   switch (opcode) {
    case SHADER_OPCODE_RCP:
    case SHADER_OPCODE_RSQ:
    case SHADER_OPCODE_SQRT:
@@ -376,7 +376,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
    case SHADER_OPCODE_TG4_OFFSET:
    case SHADER_OPCODE_SAMPLEINFO:
    case SHADER_OPCODE_GET_BUFFER_SIZE:
-      return inst->header_size;
+      return header_size;
    default:
       unreachable("not reached");
    }

src/intel/compiler/brw_vec4.h

@@ -224,8 +224,6 @@ public:
 #undef EMIT2
 #undef EMIT3
 
-   int implied_mrf_writes(vec4_instruction *inst);
-
    vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
                                  src_reg src0, src_reg src1);