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intel/vec4: Make implied_mrf_writes() a vec4_instruction method

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Same as commit c20dc9b836 (intel/fs: Make implied_mrf_writes() an
fs_inst method.)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
This commit is contained in:
Matt Turner
2020-02-27 16:46:52 -08:00
committed by Marge Bot
parent d8f3d0a3a8
commit 3d0821a216
4 changed files with 8 additions and 9 deletions
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1
src/intel/compiler/brw_ir_vec4.h
View File

@@ -295,6 +295,7 @@ public:
bool can_do_writemask(const struct gen_device_info *devinfo); bool can_do_writemask(const struct gen_device_info *devinfo);
bool can_change_types() const; bool can_change_types() const;
bool has_source_and_destination_hazard() const; bool has_source_and_destination_hazard() const;
unsigned implied_mrf_writes() const;
bool is_align1_partial_write() bool is_align1_partial_write()
{ {

4
src/intel/compiler/brw_schedule_instructions.cpp
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@@ -1418,7 +1418,7 @@ vec4_instruction_scheduler::calculate_deps()
} }
if (inst->mlen > 0 && !inst->is_send_from_grf()) { if (inst->mlen > 0 && !inst->is_send_from_grf()) {
for (int i = 0; i < v->implied_mrf_writes(inst); i++) { for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
add_dep(last_mrf_write[inst->base_mrf + i], n); add_dep(last_mrf_write[inst->base_mrf + i], n);
last_mrf_write[inst->base_mrf + i] = n; last_mrf_write[inst->base_mrf + i] = n;
} }
@@ -1495,7 +1495,7 @@ vec4_instruction_scheduler::calculate_deps()
} }
if (inst->mlen > 0 && !inst->is_send_from_grf()) { if (inst->mlen > 0 && !inst->is_send_from_grf()) {
for (int i = 0; i < v->implied_mrf_writes(inst); i++) { for (unsigned i = 0; i < inst->implied_mrf_writes(); i++) {
last_mrf_write[inst->base_mrf + i] = n; last_mrf_write[inst->base_mrf + i] = n;
} }
} }

10
src/intel/compiler/brw_vec4.cpp
View File

@@ -326,13 +326,13 @@ vec4_instruction::can_change_types() const
* instruction -- the generate_* functions generate additional MOVs * instruction -- the generate_* functions generate additional MOVs
* for setup. * for setup.
*/ */
int unsigned
vec4_visitor::implied_mrf_writes(vec4_instruction *inst) vec4_instruction::implied_mrf_writes() const
{ {
if (inst->mlen == 0 || inst->is_send_from_grf()) if (mlen == 0 || is_send_from_grf())
return 0; return 0;
switch (inst->opcode) { switch (opcode) {
case SHADER_OPCODE_RCP: case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ: case SHADER_OPCODE_RSQ:
case SHADER_OPCODE_SQRT: case SHADER_OPCODE_SQRT:
@@ -376,7 +376,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
case SHADER_OPCODE_TG4_OFFSET: case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO: case SHADER_OPCODE_SAMPLEINFO:
case SHADER_OPCODE_GET_BUFFER_SIZE: case SHADER_OPCODE_GET_BUFFER_SIZE:
return inst->header_size; return header_size;
default: default:
unreachable("not reached"); unreachable("not reached");
} }

2
src/intel/compiler/brw_vec4.h
View File

@@ -224,8 +224,6 @@ public:
#undef EMIT2 #undef EMIT2
#undef EMIT3 #undef EMIT3
int implied_mrf_writes(vec4_instruction *inst);
vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst, vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
src_reg src0, src_reg src1); src_reg src0, src_reg src1);