intel/fs: fixup scratch load/store handling on Gfx12.5+
We did not handle the operation with data size < 4. It works fine on
all other messages (global/shared). The initial commit was just too
restrictive.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1e242785c3
("intel/fs: Implement load/store_scratch on XeHP")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16964>
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3c78e94ff3
@@ -5190,24 +5190,26 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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assert(nir_dest_num_components(instr->dest) == 1);
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assert(nir_dest_bit_size(instr->dest) <= 32);
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assert(nir_intrinsic_align(instr) > 0);
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if (devinfo->verx10 >= 125) {
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assert(nir_dest_bit_size(instr->dest) == 32 &&
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nir_intrinsic_align(instr) >= 4);
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if (nir_dest_bit_size(instr->dest) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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if (devinfo->verx10 >= 125) {
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assert(nir_dest_bit_size(instr->dest) == 32 &&
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nir_intrinsic_align(instr) >= 4);
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, false);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1);
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, false);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1);
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bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else if (nir_dest_bit_size(instr->dest) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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/* The offset for a DWORD scattered message is in dwords. */
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, true);
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bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else {
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/* The offset for a DWORD scattered message is in dwords. */
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, true);
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bld.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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bld.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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}
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} else {
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, false);
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@@ -5261,27 +5263,27 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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assert(nir_src_bit_size(instr->src[0]) <= 32);
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assert(nir_intrinsic_write_mask(instr) == 1);
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assert(nir_intrinsic_align(instr) > 0);
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if (devinfo->verx10 >= 125) {
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assert(nir_src_bit_size(instr->src[0]) == 32 &&
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nir_intrinsic_align(instr) >= 4);
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srcs[SURFACE_LOGICAL_SRC_DATA] = data;
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if (nir_src_bit_size(instr->src[0]) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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if (devinfo->verx10 >= 125) {
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srcs[SURFACE_LOGICAL_SRC_DATA] = data;
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, false);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1);
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, false);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1);
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bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else if (nir_src_bit_size(instr->src[0]) == 32 &&
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nir_intrinsic_align(instr) >= 4) {
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srcs[SURFACE_LOGICAL_SRC_DATA] = data;
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bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
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dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else {
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srcs[SURFACE_LOGICAL_SRC_DATA] = data;
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/* The offset for a DWORD scattered message is in dwords. */
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, true);
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/* The offset for a DWORD scattered message is in dwords. */
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srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
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swizzle_nir_scratch_addr(bld, nir_addr, true);
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bld.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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bld.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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}
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} else {
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srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD);
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bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data);
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