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intel/fs: fixup SEND validation check on overlapping src0/src1

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With the following SEND instruction :

   send(1)         nullUD          nullUD          g0UD            0x4200c504                a0.1<0>UD

This instruction although valid but somewhat nonsensical (SEND message
to write at offset contained in NULL register), triggers an error in
the validator.

The restriction is that we cannot have overlapping sources. The
validator not checking the type of register incorrectly thinks that
the null register (offset 0) is the same as g0.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
This commit is contained in:
Lionel Landwerlin
2022-07-24 13:05:57 +03:00
committed by Marge Bot
parent a81ca32f96
commit 3c6fa2703d
1 changed files with 2 additions and 1 deletions
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3
src/intel/compiler/brw_eu_validate.c
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@@ -435,7 +435,8 @@ send_restrictions(const struct brw_isa_info *isa,
brw_inst_send_src1_reg_nr(devinfo, inst) < 112,
"send with EOT must use g112-g127");
if (brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE) {
if (brw_inst_send_src0_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE &&
brw_inst_send_src1_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE) {
/* Assume minimums if we don't know */
unsigned mlen = 1;
if (!brw_inst_send_sel_reg32_desc(devinfo, inst)) {