anv/gen7: Implement the VS state depth-stall workaround
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@@ -667,6 +667,8 @@ VkResult anv_CreateDevice(
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anv_state_pool_init(&device->surface_state_pool,
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anv_state_pool_init(&device->surface_state_pool,
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&device->surface_state_block_pool);
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&device->surface_state_block_pool);
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anv_bo_init_new(&device->workaround_bo, device, 1024);
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anv_block_pool_init(&device->scratch_block_pool, device, 0x10000);
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anv_block_pool_init(&device->scratch_block_pool, device, 0x10000);
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device->info = *physical_device->info;
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device->info = *physical_device->info;
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@@ -705,6 +707,9 @@ void anv_DestroyDevice(
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anv_state_pool_free(&device->dynamic_state_pool, device->border_colors);
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anv_state_pool_free(&device->dynamic_state_pool, device->border_colors);
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#endif
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#endif
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anv_gem_munmap(device->workaround_bo.map, device->workaround_bo.size);
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anv_gem_close(device, device->workaround_bo.gem_handle);
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anv_bo_pool_finish(&device->batch_bo_pool);
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anv_bo_pool_finish(&device->batch_bo_pool);
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anv_state_pool_finish(&device->dynamic_state_pool);
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anv_state_pool_finish(&device->dynamic_state_pool);
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anv_block_pool_finish(&device->dynamic_state_block_pool);
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anv_block_pool_finish(&device->dynamic_state_block_pool);
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@@ -497,6 +497,8 @@ struct anv_device {
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struct anv_block_pool surface_state_block_pool;
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struct anv_block_pool surface_state_block_pool;
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struct anv_state_pool surface_state_pool;
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struct anv_state_pool surface_state_pool;
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struct anv_bo workaround_bo;
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struct anv_meta_state meta_state;
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struct anv_meta_state meta_state;
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struct anv_state border_colors;
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struct anv_state border_colors;
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@@ -287,6 +287,24 @@ gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer)
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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}
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}
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if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT ||
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cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) {
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/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
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*
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* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
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* stall needs to be sent just prior to any 3DSTATE_VS,
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* 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
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* 3DSTATE_BINDING_TABLE_POINTER_VS,
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* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
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* PIPE_CONTROL needs to be sent before any combination of VS
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* associated 3DSTATE."
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*/
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anv_batch_emit(&cmd_buffer->batch, GEN7_PIPE_CONTROL,
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.DepthStallEnable = true,
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.PostSyncOperation = WriteImmediateData,
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.Address = { &cmd_buffer->device->workaround_bo, 0 });
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}
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if (cmd_buffer->state.descriptors_dirty)
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if (cmd_buffer->state.descriptors_dirty)
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anv_flush_descriptor_sets(cmd_buffer);
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anv_flush_descriptor_sets(cmd_buffer);
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@@ -380,6 +380,19 @@ gen7_graphics_pipeline_create(
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false);
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/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
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*
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* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
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* needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
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* 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
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* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
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* needs to be sent before any combination of VS associated 3DSTATE."
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*/
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anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL,
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.DepthStallEnable = true,
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.PostSyncOperation = WriteImmediateData,
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.Address = { &device->workaround_bo, 0 });
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
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anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
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.ConstantBufferOffset = 0,
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.ConstantBufferOffset = 0,
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.ConstantBufferSize = 4);
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.ConstantBufferSize = 4);
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