radv: set image_dim and image_array intrinsic indices

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12190>
This commit is contained in:
Rhys Perry
2021-07-30 13:25:26 +01:00
committed by Marge Bot
parent 513f9b5dc9
commit 39db5a569b
5 changed files with 20 additions and 14 deletions

View File

@@ -92,7 +92,8 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d)
nir_ssa_def *outval = &tex->dest.ssa;
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord,
nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0),
.image_dim = GLSL_SAMPLER_DIM_BUF);
return b.shader;
}
@@ -279,7 +280,7 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d)
nir_ssa_def *outval = &tex->dest.ssa;
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, img_coord,
nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0), .image_dim = dim);
return b.shader;
}
@@ -472,7 +473,7 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev)
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord,
nir_ssa_undef(&b, 1, 32), nir_channel(&b, outval, chan),
nir_imm_int(&b, 0));
nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_BUF);
}
return b.shader;
@@ -628,7 +629,7 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d, int samples)
for (uint32_t i = 0; i < samples; i++) {
nir_ssa_def *outval = &tex_instr[i]->dest.ssa;
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, dst_coord,
nir_imm_int(&b, i), outval, nir_imm_int(&b, 0));
nir_imm_int(&b, i), outval, nir_imm_int(&b, 0), .image_dim = dim);
}
return b.shader;
@@ -843,7 +844,7 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev)
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, dst_coord,
nir_ssa_undef(&b, 1, 32), nir_channel(&b, outval, 0),
nir_imm_int(&b, 0));
nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_BUF);
}
return b.shader;
@@ -972,7 +973,7 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples
for (uint32_t i = 0; i < samples; i++) {
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, global_id,
nir_imm_int(&b, i), clear_val, nir_imm_int(&b, 0));
nir_imm_int(&b, i), clear_val, nir_imm_int(&b, 0), .image_dim = dim);
}
return b.shader;
@@ -1140,7 +1141,7 @@ build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev)
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord,
nir_ssa_undef(&b, 1, 32), nir_channel(&b, clear_val, chan),
nir_imm_int(&b, 0));
nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_BUF);
}
return b.shader;

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@@ -93,6 +93,7 @@ build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *sur
dcc_val->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
dcc_val->src[3] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_ssa_dest_init(&dcc_val->instr, &dcc_val->dest, 1, 32, "dcc_val");
nir_intrinsic_set_image_dim(dcc_val, GLSL_SAMPLER_DIM_BUF);
nir_builder_instr_insert(&b, &dcc_val->instr);
nir_intrinsic_instr *store =
@@ -103,6 +104,7 @@ build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *sur
store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
store->src[3] = nir_src_for_ssa(&dcc_val->dest.ssa);
store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0));
nir_intrinsic_set_image_dim(store, GLSL_SAMPLER_DIM_BUF);
nir_builder_instr_insert(&b, &store->instr);
return b.shader;

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@@ -56,9 +56,9 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
nir_ssa_def *data =
nir_image_deref_load(&b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, global_id,
nir_ssa_undef(&b, 1, 32), nir_imm_int(&b, 0));
nir_ssa_def *data = nir_image_deref_load(
&b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, global_id, nir_ssa_undef(&b, 1, 32),
nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_2D);
/* We need a NIR_SCOPE_DEVICE memory_scope because ACO will avoid
* creating a vmcnt(0) because it expects the L1 cache to keep memory
@@ -68,7 +68,8 @@ build_dcc_decompress_compute_shader(struct radv_device *dev)
.memory_semantics = NIR_MEMORY_ACQ_REL, .memory_modes = nir_var_mem_ssbo);
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, global_id,
nir_ssa_undef(&b, 1, 32), data, nir_imm_int(&b, 0));
nir_ssa_undef(&b, 1, 32), data, nir_imm_int(&b, 0),
.image_dim = GLSL_SAMPLER_DIM_2D);
return b.shader;
}

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@@ -92,7 +92,7 @@ build_fmask_expand_compute_shader(struct radv_device *device, int samples)
nir_ssa_def *outval = &tex_instr[i]->dest.ssa;
nir_image_deref_store(&b, output_img_deref, img_coord, nir_imm_int(&b, i), outval,
nir_imm_int(&b, 0));
nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_MS, .image_array = true);
}
return b.shader;

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@@ -100,7 +100,8 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s
nir_ssa_def *coord = nir_iadd(&b, global_id, dst_offset);
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord,
nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0),
.image_dim = GLSL_SAMPLER_DIM_2D);
return b.shader;
}
@@ -229,7 +230,8 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
nir_ssa_def *coord = nir_vec4(&b, nir_channel(&b, img_coord, 0), nir_channel(&b, img_coord, 1),
nir_channel(&b, img_coord, 2), nir_imm_int(&b, 0));
nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord,
nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0));
nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0),
.image_dim = GLSL_SAMPLER_DIM_2D, .image_array = true);
return b.shader;
}