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intel/fs: Drop support for nir_register

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Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104>
This commit is contained in:
Faith Ekstrand
2023-07-12 02:37:17 -05:00
committed by Marge Bot
parent ce75c3c3fe
commit 39b5bb0809
3 changed files with 37 additions and 64 deletions
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1
src/intel/compiler/brw_fs.h
View File

@@ -475,7 +475,6 @@ public:
/** Either BRW_MAX_GRF or GFX7_MRF_HACK_START */
unsigned max_grf;
fs_reg *nir_locals;
fs_reg *nir_ssa_values;
fs_inst **nir_resource_insts;
struct brw_fs_bind_info *nir_ssa_bind_infos;

33
src/intel/compiler/brw_fs_nir.cpp
View File

@@ -306,20 +306,6 @@ fs_visitor::nir_emit_system_values()
void
fs_visitor::nir_emit_impl(nir_function_impl *impl)
{
nir_locals = ralloc_array(mem_ctx, fs_reg, impl->reg_alloc);
for (unsigned i = 0; i < impl->reg_alloc; i++) {
nir_locals[i] = fs_reg();
}
foreach_list_typed(nir_register, reg, node, &impl->registers) {
unsigned array_elems =
reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
unsigned size = array_elems * reg->num_components;
const brw_reg_type reg_type = reg->bit_size == 8 ? BRW_REGISTER_TYPE_B :
brw_reg_type_from_bit_size(reg->bit_size, BRW_REGISTER_TYPE_F);
nir_locals[reg->index] = bld.vgrf(reg_type, size);
}
nir_ssa_values = reralloc(mem_ctx, nir_ssa_values, fs_reg,
impl->ssa_alloc);
@@ -2014,9 +2000,10 @@ fs_visitor::get_resource_nir_src(const nir_src &src)
fs_reg
fs_visitor::get_nir_src(const nir_src &src)
{
fs_reg reg;
if (src.is_ssa) {
assert(src.is_ssa);
nir_intrinsic_instr *load_reg = nir_load_reg_for_def(src.ssa);
fs_reg reg;
if (!load_reg) {
if (nir_src_is_undef(src)) {
const brw_reg_type reg_type =
@@ -2036,12 +2023,6 @@ fs_visitor::get_nir_src(const nir_src &src)
reg = offset(nir_ssa_values[decl_reg->dest.ssa.index], bld,
src.reg.base_offset * num_components);
}
} else {
/* We don't handle indirects on locals */
assert(src.reg.indirect == NULL);
reg = offset(nir_locals[src.reg.reg->index], bld,
src.reg.base_offset * src.reg.reg->num_components);
}
if (nir_src_bit_size(src) == 64 && devinfo->ver == 7) {
/* The only 64-bit type available on gfx7 is DF, so use that. */
@@ -2078,7 +2059,7 @@ fs_visitor::get_nir_src_imm(const nir_src &src)
fs_reg
fs_visitor::get_nir_dest(const nir_dest &dest)
{
if (dest.is_ssa) {
assert(dest.is_ssa);
nir_intrinsic_instr *store_reg = nir_store_reg_for_def(&dest.ssa);
if (!store_reg) {
const brw_reg_type reg_type =
@@ -2101,12 +2082,6 @@ fs_visitor::get_nir_dest(const nir_dest &dest)
return offset(nir_ssa_values[decl_reg->dest.ssa.index], bld,
dest.reg.base_offset * num_components);
}
} else {
/* We don't handle indirects on locals */
assert(dest.reg.indirect == NULL);
return offset(nir_locals[dest.reg.reg->index], bld,
dest.reg.base_offset * dest.reg.reg->num_components);
}
}
static fs_inst *

1
src/intel/compiler/brw_fs_visitor.cpp
View File

@@ -1410,7 +1410,6 @@ fs_visitor::init()
this->failed = false;
this->fail_msg = NULL;
this->nir_locals = NULL;
this->nir_ssa_values = NULL;
this->nir_resource_insts = NULL;
this->nir_ssa_bind_infos = NULL;