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amd: change chip_class naming to "enum amd_gfx_level gfx_level"

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This aligns the naming with PAL.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
This commit is contained in:
Marek Olšák
2022-05-12 02:50:17 -04:00
parent 6dcf7f651f
commit 39800f0fa3
198 changed files with 2775 additions and 2776 deletions
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224
src/amd/vulkan/radv_pipeline.c
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@@ -1183,7 +1183,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(
pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
pipeline->device->physical_device->rad_info.gfx_level >= GFX9) |
S_028A48_VPORT_SCISSOR_ENABLE(1);
const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line = vk_find_struct_const(
@@ -1217,7 +1217,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
S_028BE0_COVERED_CENTROID_IS_CENTER(
pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3);
ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
if (ps_iter_samples > 1)
pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
@@ -1500,7 +1500,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline)
/* GS requirement. */
ia_multi_vgt_param.partial_es_wave = false;
if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.gfx_level <= GFX8)
if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
ia_multi_vgt_param.partial_es_wave = true;
@@ -1527,7 +1527,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline)
/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
if (device->physical_device->rad_info.has_distributed_tess) {
if (radv_pipeline_has_gs(pipeline)) {
if (device->physical_device->rad_info.chip_class <= GFX8)
if (device->physical_device->rad_info.gfx_level <= GFX8)
ia_multi_vgt_param.partial_es_wave = true;
} else {
ia_multi_vgt_param.partial_vs_wave = true;
@@ -1558,9 +1558,9 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline)
ia_multi_vgt_param.base =
S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
/* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.gfx_level == GFX8 ? 2 : 0) |
S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.gfx_level >= GFX9) |
S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.gfx_level >= GFX9);
return ia_multi_vgt_param;
}
@@ -1963,7 +1963,7 @@ radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
S_028814_POLY_OFFSET_PARA_ENABLE(raster_info->depthBiasEnable ? 1 : 0) |
S_028814_PROVOKING_VTX_LAST(provoking_vtx_last);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
/* It should also be set if PERPENDICULAR_ENDCAP_ENA is set. */
pipeline->graphics.pa_su_sc_mode_cntl |=
S_028814_KEEP_TOGETHER_ENABLE(raster_info->polygonMode != VK_POLYGON_MODE_FILL);
@@ -2026,7 +2026,7 @@ radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
/* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
ds_state.db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(vkms && vkms->rasterizationSamples > 2);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3)
ds_state.db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE(1);
db_depth_control = S_028800_Z_ENABLE(ds_info->depthTestEnable ? 1 : 0) |
@@ -2071,7 +2071,7 @@ gfx9_get_gs_info(const struct radv_pipeline_key *key, const struct radv_pipeline
struct radv_shader_info *gs_info = &stages[MESA_SHADER_GEOMETRY].info;
struct radv_es_output_info *es_info;
bool has_tess = !!stages[MESA_SHADER_TESS_CTRL].nir;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9)
es_info = has_tess ? &gs_info->tes.es_info : &gs_info->vs.es_info;
else
es_info = has_tess ? &stages[MESA_SHADER_TESS_EVAL].info.tes.es_info
@@ -2180,10 +2180,9 @@ gfx9_get_gs_info(const struct radv_pipeline_key *key, const struct radv_pipeline
assert(max_prims_per_subgroup <= max_out_prims);
gl_shader_stage es_stage = has_tess ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
unsigned workgroup_size =
ac_compute_esgs_workgroup_size(
pipeline->device->physical_device->rad_info.chip_class, stages[es_stage].info.wave_size,
es_verts_per_subgroup, gs_inst_prims_in_subgroup);
unsigned workgroup_size = ac_compute_esgs_workgroup_size(
pipeline->device->physical_device->rad_info.gfx_level, stages[es_stage].info.wave_size,
es_verts_per_subgroup, gs_inst_prims_in_subgroup);
stages[es_stage].info.workgroup_size = workgroup_size;
stages[MESA_SHADER_GEOMETRY].info.workgroup_size = workgroup_size;
}
@@ -2221,7 +2220,8 @@ radv_get_num_input_vertices(const struct radv_pipeline_stage *stages)
}
static void
gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t oversub_pc_lines)
gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level,
uint32_t oversub_pc_lines)
{
radeon_set_uconfig_reg(
cs, R_030980_GE_PC_ALLOC,
@@ -2318,7 +2318,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi
/* All these are per subgroup: */
const unsigned min_esverts =
pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 29 : 24;
pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3 ? 29 : 24;
bool max_vert_out_per_gs_instance = false;
unsigned max_esverts_base = 128;
unsigned max_gsprims_base = 128; /* default prim group size clamp */
@@ -2425,7 +2425,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi
max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
/* Hardware restriction: minimum value of max_esverts */
if (pipeline->device->physical_device->rad_info.chip_class == GFX10)
if (pipeline->device->physical_device->rad_info.gfx_level == GFX10)
max_esverts = MAX2(max_esverts, min_esverts - 1 + max_verts_per_prim);
else
max_esverts = MAX2(max_esverts, min_esverts);
@@ -2448,13 +2448,13 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi
} while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
/* Verify the restriction. */
if (pipeline->device->physical_device->rad_info.chip_class == GFX10)
if (pipeline->device->physical_device->rad_info.gfx_level == GFX10)
assert(max_esverts >= min_esverts - 1 + max_verts_per_prim);
else
assert(max_esverts >= min_esverts);
} else {
/* Hardware restriction: minimum value of max_esverts */
if (pipeline->device->physical_device->rad_info.chip_class == GFX10)
if (pipeline->device->physical_device->rad_info.gfx_level == GFX10)
max_esverts = MAX2(max_esverts, min_esverts - 1 + max_verts_per_prim);
else
max_esverts = MAX2(max_esverts, min_esverts);
@@ -2478,7 +2478,7 @@ gfx10_get_ngg_info(const struct radv_pipeline_key *key, struct radv_pipeline *pi
* whenever this check passes, there is enough space for a full
* primitive without vertex reuse.
*/
if (pipeline->device->physical_device->rad_info.chip_class == GFX10)
if (pipeline->device->physical_device->rad_info.gfx_level == GFX10)
ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
else
ngg->hw_max_esverts = max_esverts;
@@ -2520,7 +2520,7 @@ radv_pipeline_init_gs_ring_state(struct radv_pipeline *pipeline, const struct gf
* On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
*/
unsigned gs_vertex_reuse =
(device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
(device->physical_device->rad_info.gfx_level >= GFX8 ? 32 : 16) * num_se;
unsigned alignment = 256 * num_se;
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
@@ -2538,7 +2538,7 @@ radv_pipeline_init_gs_ring_state(struct radv_pipeline *pipeline, const struct gf
esgs_ring_size = align(esgs_ring_size, alignment);
gsvs_ring_size = align(gsvs_ring_size, alignment);
if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
if (pipeline->device->physical_device->rad_info.gfx_level <= GFX8)
pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
@@ -2747,7 +2747,7 @@ radv_link_shaders(struct radv_pipeline *pipeline,
bool has_geom_tess = stages[MESA_SHADER_GEOMETRY].nir || stages[MESA_SHADER_TESS_CTRL].nir;
bool merged_gs = stages[MESA_SHADER_GEOMETRY].nir &&
pipeline->device->physical_device->rad_info.chip_class >= GFX9;
pipeline->device->physical_device->rad_info.gfx_level >= GFX9;
if (!optimize_conservatively && shader_count > 1) {
unsigned first = ordered_shaders[shader_count - 1]->info.stage;
@@ -2923,7 +2923,7 @@ radv_link_shaders(struct radv_pipeline *pipeline,
if (progress) {
if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
ac_nir_lower_indirect_derefs(ordered_shaders[i],
pipeline->device->physical_device->rad_info.chip_class);
pipeline->device->physical_device->rad_info.gfx_level);
/* remove dead writes, which can remove input loads */
nir_lower_vars_to_ssa(ordered_shaders[i]);
nir_opt_dce(ordered_shaders[i]);
@@ -2931,7 +2931,7 @@ radv_link_shaders(struct radv_pipeline *pipeline,
if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
ac_nir_lower_indirect_derefs(ordered_shaders[i - 1],
pipeline->device->physical_device->rad_info.chip_class);
pipeline->device->physical_device->rad_info.gfx_level);
}
}
}
@@ -2991,7 +2991,7 @@ radv_set_driver_locations(struct radv_pipeline *pipeline, struct radv_pipeline_s
unsigned vs_info_idx = MESA_SHADER_VERTEX;
unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) {
/* These are merged into the next stage */
vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
@@ -3059,10 +3059,10 @@ radv_generate_pipeline_key(const struct radv_pipeline *pipeline, VkPipelineCreat
key.optimisations_disabled = 1;
key.disable_aniso_single_level = device->instance->disable_aniso_single_level &&
device->physical_device->rad_info.chip_class < GFX8;
device->physical_device->rad_info.gfx_level < GFX8;
key.image_2d_view_of_3d = device->image_2d_view_of_3d &&
device->physical_device->rad_info.chip_class == GFX9;
device->physical_device->rad_info.gfx_level == GFX9;
return key;
}
@@ -3119,17 +3119,17 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
key.ps.col_format = blend->spi_shader_col_format;
key.ps.cb_target_mask = blend->cb_target_mask;
key.ps.mrt0_is_dual_src = blend->mrt0_is_dual_src;
if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
if (pipeline->device->physical_device->rad_info.gfx_level < GFX8) {
key.ps.is_int8 = blend->col_format_is_int8;
key.ps.is_int10 = blend->col_format_is_int10;
}
if (pipeline->device->physical_device->rad_info.chip_class >= GFX11) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX11) {
key.ps.alpha_to_coverage_via_mrtz = G_028B70_ALPHA_TO_MASK_ENABLE(blend->db_alpha_to_mask);
}
key.vs.topology = vi_info->primitive_topology;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
const VkPipelineRasterizationStateCreateInfo *raster_info = pCreateInfo->pRasterizationState;
const VkPipelineRasterizationProvokingVertexStateCreateInfoEXT *provoking_vtx_info =
vk_find_struct_const(raster_info->pNext,
@@ -3348,7 +3348,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
filled_stages |= (1 << MESA_SHADER_FRAGMENT);
}
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9 &&
stages[MESA_SHADER_TESS_CTRL].nir) {
struct nir_shader *combined_nir[] = {stages[MESA_SHADER_VERTEX].nir, stages[MESA_SHADER_TESS_CTRL].nir};
@@ -3366,7 +3366,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
}
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9 &&
stages[MESA_SHADER_GEOMETRY].nir) {
gl_shader_stage pre_stage =
stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
@@ -3453,7 +3453,7 @@ static void
radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stage *stages,
const struct radv_pipeline_key *pipeline_key)
{
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
unsigned active_stages = 0;
for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; i++) {
@@ -3468,8 +3468,8 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
stages[i].args.load_grid_size_from_user_sgpr = device->load_grid_size_from_user_sgpr;
}
if (chip_class >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) {
radv_declare_shader_args(chip_class, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info,
if (gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) {
radv_declare_shader_args(gfx_level, pipeline_key, &stages[MESA_SHADER_TESS_CTRL].info,
MESA_SHADER_TESS_CTRL, true, MESA_SHADER_VERTEX,
&stages[MESA_SHADER_TESS_CTRL].args);
stages[MESA_SHADER_TESS_CTRL].info.user_sgprs_locs = stages[MESA_SHADER_TESS_CTRL].args.user_sgprs_locs;
@@ -3481,11 +3481,12 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
active_stages &= ~(1 << MESA_SHADER_TESS_CTRL);
}
if (chip_class >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) {
if (gfx_level >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) {
gl_shader_stage pre_stage =
stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
radv_declare_shader_args(chip_class, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info,
MESA_SHADER_GEOMETRY, true, pre_stage, &stages[MESA_SHADER_GEOMETRY].args);
radv_declare_shader_args(gfx_level, pipeline_key, &stages[MESA_SHADER_GEOMETRY].info,
MESA_SHADER_GEOMETRY, true, pre_stage,
&stages[MESA_SHADER_GEOMETRY].args);
stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs;
stages[MESA_SHADER_GEOMETRY].info.inline_push_constant_mask =
stages[MESA_SHADER_GEOMETRY].args.ac.inline_push_const_mask;
@@ -3496,8 +3497,8 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_pipeline_stag
}
u_foreach_bit(i, active_stages) {
radv_declare_shader_args(chip_class, pipeline_key, &stages[i].info, i, false, MESA_SHADER_VERTEX,
&stages[i].args);
radv_declare_shader_args(gfx_level, pipeline_key, &stages[i].info, i, false,
MESA_SHADER_VERTEX, &stages[i].args);
stages[i].info.user_sgprs_locs = stages[i].args.user_sgprs_locs;
stages[i].info.inline_push_constant_mask = stages[i].args.ac.inline_push_const_mask;
}
@@ -3572,12 +3573,13 @@ gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages,
tess_in_patch_size, tess_out_patch_size,
stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs,
stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_outputs,
stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs, device->hs.tess_offchip_block_dw_size,
device->physical_device->rad_info.chip_class, device->physical_device->rad_info.family);
stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs,
device->hs.tess_offchip_block_dw_size, device->physical_device->rad_info.gfx_level,
device->physical_device->rad_info.family);
/* LDS size used by VS+TCS for storing TCS inputs and outputs. */
unsigned tcs_lds_size = calculate_tess_lds_size(
device->physical_device->rad_info.chip_class, tess_in_patch_size, tess_out_patch_size,
device->physical_device->rad_info.gfx_level, tess_in_patch_size, tess_out_patch_size,
stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_inputs, num_patches,
stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_outputs,
stages[MESA_SHADER_TESS_CTRL].info.tcs.num_linked_patch_outputs);
@@ -3608,7 +3610,7 @@ gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages,
* doesn't handle a instruction dominating another with a different mode.
*/
stages[MESA_SHADER_VERTEX].info.vs.tcs_in_out_eq =
device->physical_device->rad_info.chip_class >= GFX9 &&
device->physical_device->rad_info.gfx_level >= GFX9 &&
tess_in_patch_size == tess_out_patch_size &&
stages[MESA_SHADER_VERTEX].nir->info.float_controls_execution_mode ==
stages[MESA_SHADER_TESS_CTRL].nir->info.float_controls_execution_mode;
@@ -3629,9 +3631,8 @@ gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages,
for (gl_shader_stage s = MESA_SHADER_VERTEX; s <= MESA_SHADER_TESS_CTRL; ++s)
stages[s].info.workgroup_size =
ac_compute_lshs_workgroup_size(
device->physical_device->rad_info.chip_class, s,
num_patches, tess_in_patch_size, tess_out_patch_size);
ac_compute_lshs_workgroup_size(device->physical_device->rad_info.gfx_level, s, num_patches,
tess_in_patch_size, tess_out_patch_size);
}
static bool
@@ -3702,7 +3703,7 @@ static unsigned
lower_bit_size_callback(const nir_instr *instr, void *_)
{
struct radv_device *device = _;
enum chip_class chip = device->physical_device->rad_info.chip_class;
enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level;
if (instr->type != nir_instr_type_alu)
return 0;
@@ -4450,7 +4451,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
/* On GFX6, read2/write2 is out-of-bounds if the offset register is negative, even if
* the final offset is not.
*/
.has_shared2_amd = device->physical_device->rad_info.chip_class >= GFX7,
.has_shared2_amd = device->physical_device->rad_info.gfx_level >= GFX7,
};
if (device->robust_buffer_access2) {
@@ -4467,7 +4468,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
}
struct radv_shader_info *info = &stages[i].info;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) {
if (i == MESA_SHADER_VERTEX && stages[MESA_SHADER_TESS_CTRL].nir)
info = &stages[MESA_SHADER_TESS_CTRL].info;
else if (i == MESA_SHADER_VERTEX && stages[MESA_SHADER_GEOMETRY].nir)
@@ -4491,7 +4492,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
nir_lower_idiv(stages[i].nir,
&(nir_lower_idiv_options){
.imprecise_32bit_lowering = false,
.allow_fp16 = device->physical_device->rad_info.chip_class >= GFX9,
.allow_fp16 = device->physical_device->rad_info.gfx_level >= GFX9,
});
nir_move_options sink_opts = nir_move_const_undef | nir_move_copies;
@@ -4509,13 +4510,13 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
radv_lower_ngg(device, &stages[i], pipeline_key);
ac_nir_lower_global_access(stages[i].nir);
radv_nir_lower_abi(stages[i].nir, device->physical_device->rad_info.chip_class,
radv_nir_lower_abi(stages[i].nir, device->physical_device->rad_info.gfx_level,
&stages[i].info, &stages[i].args, pipeline_key);
radv_optimize_nir_algebraic(
stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE || i == MESA_SHADER_TASK);
if (stages[i].nir->info.bit_sizes_int & (8 | 16)) {
if (device->physical_device->rad_info.chip_class >= GFX8) {
if (device->physical_device->rad_info.gfx_level >= GFX8) {
nir_convert_to_lcssa(stages[i].nir, true, true);
nir_divergence_analysis(stages[i].nir);
}
@@ -4525,11 +4526,11 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
NIR_PASS_V(stages[i].nir, nir_opt_dce);
}
if (device->physical_device->rad_info.chip_class >= GFX8)
if (device->physical_device->rad_info.gfx_level >= GFX8)
nir_opt_remove_phis(stages[i].nir); /* cleanup LCSSA phis */
}
if (((stages[i].nir->info.bit_sizes_int | stages[i].nir->info.bit_sizes_float) & 16) &&
device->physical_device->rad_info.chip_class >= GFX9) {
device->physical_device->rad_info.gfx_level >= GFX9) {
bool copy_prop = false;
uint32_t sampler_dims = UINT32_MAX;
/* Skip because AMD doesn't support 16-bit types with these. */
@@ -4547,7 +4548,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
NIR_PASS_V(stages[i].nir, nir_opt_vectorize, opt_vectorize_callback, NULL);
}
}
/* cleanup passes */
nir_lower_load_const_to_scalar(stages[i].nir);
@@ -4585,7 +4586,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
struct radv_shader_args gs_copy_args = {0};
gs_copy_args.is_gs_copy_shader = true;
gs_copy_args.explicit_scratch_args = !radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX);
radv_declare_shader_args(device->physical_device->rad_info.chip_class, pipeline_key, &info,
radv_declare_shader_args(device->physical_device->rad_info.gfx_level, pipeline_key, &info,
MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX, &gs_copy_args);
info.user_sgprs_locs = gs_copy_args.user_sgprs_locs;
info.inline_push_constant_mask = gs_copy_args.ac.inline_push_const_mask;
@@ -4615,7 +4616,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
active_stages &= ~(1 << MESA_SHADER_FRAGMENT);
}
if (device->physical_device->rad_info.chip_class >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) {
if (device->physical_device->rad_info.gfx_level >= GFX9 && stages[MESA_SHADER_TESS_CTRL].nir) {
if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
struct nir_shader *combined_nir[] = {stages[MESA_SHADER_VERTEX].nir, stages[MESA_SHADER_TESS_CTRL].nir};
int64_t stage_start = os_time_get_nano();
@@ -4631,7 +4632,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
active_stages &= ~(1 << MESA_SHADER_TESS_CTRL);
}
if (device->physical_device->rad_info.chip_class >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) {
if (device->physical_device->rad_info.gfx_level >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) {
gl_shader_stage pre_stage =
stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
@@ -4731,7 +4732,7 @@ done:
static uint32_t
radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, gl_shader_stage stage,
enum chip_class chip_class)
enum amd_gfx_level gfx_level)
{
bool has_gs = radv_pipeline_has_gs(pipeline);
bool has_tess = radv_pipeline_has_tess(pipeline);
@@ -4742,9 +4743,9 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, gl_shader_sta
return R_00B030_SPI_SHADER_USER_DATA_PS_0;
case MESA_SHADER_VERTEX:
if (has_tess) {
if (chip_class >= GFX10) {
if (gfx_level >= GFX10) {
return R_00B430_SPI_SHADER_USER_DATA_HS_0;
} else if (chip_class == GFX9) {
} else if (gfx_level == GFX9) {
return R_00B430_SPI_SHADER_USER_DATA_LS_0;
} else {
return R_00B530_SPI_SHADER_USER_DATA_LS_0;
@@ -4752,7 +4753,7 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, gl_shader_sta
}
if (has_gs) {
if (chip_class >= GFX10) {
if (gfx_level >= GFX10) {
return R_00B230_SPI_SHADER_USER_DATA_GS_0;
} else {
return R_00B330_SPI_SHADER_USER_DATA_ES_0;
@@ -4764,18 +4765,18 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline, gl_shader_sta
return R_00B130_SPI_SHADER_USER_DATA_VS_0;
case MESA_SHADER_GEOMETRY:
return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B230_SPI_SHADER_USER_DATA_GS_0;
return gfx_level == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0
: R_00B230_SPI_SHADER_USER_DATA_GS_0;
case MESA_SHADER_COMPUTE:
case MESA_SHADER_TASK:
return R_00B900_COMPUTE_USER_DATA_0;
case MESA_SHADER_TESS_CTRL:
return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0
: R_00B430_SPI_SHADER_USER_DATA_HS_0;
return gfx_level == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0
: R_00B430_SPI_SHADER_USER_DATA_HS_0;
case MESA_SHADER_TESS_EVAL:
if (has_gs) {
return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0
: R_00B330_SPI_SHADER_USER_DATA_ES_0;
return gfx_level >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0
: R_00B330_SPI_SHADER_USER_DATA_ES_0;
} else if (has_ngg) {
return R_00B230_SPI_SHADER_USER_DATA_GS_0;
} else {
@@ -5168,7 +5169,7 @@ radv_pipeline_init_disabled_binning_state(struct radv_pipeline *pipeline,
uint32_t pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
S_028C44_DISABLE_START_OF_PRIM(1);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
const VkPipelineColorBlendStateCreateInfo *vkblend =
@@ -5232,13 +5233,13 @@ radv_pipeline_init_binning_state(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_blend_state *blend)
{
if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
if (pipeline->device->physical_device->rad_info.gfx_level < GFX9)
return;
VkExtent2D bin_size;
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
} else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
} else if (pipeline->device->physical_device->rad_info.gfx_level == GFX9) {
bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
} else
unreachable("Unhandled generation for binning bin size calculation");
@@ -5302,7 +5303,7 @@ radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
const VkConservativeRasterizationModeEXT mode = radv_get_conservative_raster_mode(vkraster);
uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) {
/* Conservative rasterization. */
if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
@@ -5348,7 +5349,7 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
* if no sample lies on the pixel boundary (-8 sample offset). It's
* currently always TRUE because the driver doesn't support 16 samples.
*/
bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
bool exclusion = pipeline->device->physical_device->rad_info.gfx_level >= GFX7;
radeon_set_context_reg(
ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
@@ -5372,7 +5373,7 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
const struct radv_shader *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
pipeline->device->physical_device->rad_info.chip_class);
pipeline->device->physical_device->rad_info.gfx_level);
} else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
@@ -5409,7 +5410,7 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
nparams = MAX2(outinfo->param_exports, 1);
spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
}
@@ -5436,15 +5437,15 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
total_mask << 8 | clip_dist_mask);
if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
if (pipeline->device->physical_device->rad_info.gfx_level <= GFX8)
radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, outinfo->writes_viewport_index);
unsigned late_alloc_wave64, cu_mask;
ac_compute_late_alloc(&pipeline->device->physical_device->rad_info, false, false,
shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX7) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
ac_set_reg_cu_en(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
S_00B118_CU_EN(cu_mask) | S_00B118_WAVE_LIMIT(0x3F),
C_00B118_CU_EN, 0, &pipeline->device->physical_device->rad_info,
@@ -5455,9 +5456,10 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
}
radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(late_alloc_wave64));
}
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
uint32_t oversub_pc_lines = late_alloc_wave64 ? pipeline->device->physical_device->rad_info.pc_lines / 4 : 0;
gfx10_emit_ge_pc_alloc(cs, pipeline->device->physical_device->rad_info.chip_class, oversub_pc_lines);
gfx10_emit_ge_pc_alloc(cs, pipeline->device->physical_device->rad_info.gfx_level,
oversub_pc_lines);
}
}
@@ -5485,7 +5487,7 @@ radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, const struct radv_pipelin
radeon_set_sh_reg(cs, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks);
if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
if (pipeline->device->physical_device->rad_info.gfx_level == GFX7 &&
pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
@@ -5604,7 +5606,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
*
* Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
*/
if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
if (pipeline->device->physical_device->rad_info.gfx_level == GFX10 &&
!radv_pipeline_has_tess(pipeline) && ngg_state->hw_max_esverts != 256) {
ge_cntl &= C_03096C_VERT_GRP_SIZE;
@@ -5619,7 +5621,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
ac_compute_late_alloc(&pipeline->device->physical_device->rad_info, true, shader->info.has_ngg_culling,
shader->config.scratch_bytes_per_wave > 0, &late_alloc_wave64, &cu_mask);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
ac_set_reg_cu_en(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
S_00B21C_CU_EN(cu_mask) | S_00B21C_WAVE_LIMIT(0x3F),
C_00B21C_CU_EN, 0, &pipeline->device->physical_device->rad_info,
@@ -5649,7 +5651,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
oversub_pc_lines *= oversub_factor;
}
gfx10_emit_ge_pc_alloc(cs, pipeline->device->physical_device->rad_info.chip_class, oversub_pc_lines);
gfx10_emit_ge_pc_alloc(cs, pipeline->device->physical_device->rad_info.gfx_level,
oversub_pc_lines);
}
static void
@@ -5658,8 +5661,8 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, const struct radv_pipelin
{
uint64_t va = radv_shader_get_va(shader);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
radeon_set_sh_reg(cs, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
} else {
radeon_set_sh_reg(cs, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
@@ -5718,7 +5721,7 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs, struct radeon_
radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10 &&
!radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
S_028A44_ES_VERTS_PER_SUBGRP(250) | S_028A44_GS_PRIMS_PER_SUBGRP(126) |
@@ -5744,7 +5747,7 @@ radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX7) {
radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
} else {
radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
@@ -5857,8 +5860,8 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
va = radv_shader_get_va(gs);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
radeon_set_sh_reg(cs, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
} else {
radeon_set_sh_reg(cs, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
@@ -5879,7 +5882,7 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
radeon_emit(cs, gs->config.rsrc2);
}
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
ac_set_reg_cu_en(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F),
C_00B21C_CU_EN, 0, &pipeline->device->physical_device->rad_info,
@@ -5888,12 +5891,12 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf
S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0),
C_00B204_CU_EN_GFX10, 16, &pipeline->device->physical_device->rad_info,
(void*)gfx10_set_sh_reg_idx3);
} else if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
} else if (pipeline->device->physical_device->rad_info.gfx_level >= GFX7) {
radeon_set_sh_reg_idx(
pipeline->device->physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, 3,
S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
radeon_set_sh_reg_idx(
pipeline->device->physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, 3,
S_00B204_CU_EN_GFX10(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
@@ -6145,7 +6148,7 @@ radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
const struct radv_pipeline *pipeline)
{
if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
pipeline->device->physical_device->rad_info.chip_class >= GFX10)
pipeline->device->physical_device->rad_info.gfx_level >= GFX10)
return;
unsigned vtx_reuse_depth = 30;
@@ -6191,10 +6194,10 @@ radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs,
stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
}
if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX9)
stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10) {
uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
if (radv_pipeline_has_tess(pipeline))
@@ -6414,11 +6417,11 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo);
radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, vgt_gs_out_prim_type);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10 &&
!radv_pipeline_has_ngg(pipeline))
gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) {
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3) {
gfx103_pipeline_generate_vgt_draw_payload_cntl(ctx_cs, pipeline, pCreateInfo);
gfx103_pipeline_generate_vrs_state(ctx_cs, pipeline, pCreateInfo);
}
@@ -6501,7 +6504,7 @@ radv_pipeline_init_shader_stages_state(struct radv_pipeline *pipeline)
if (shader_exists || i < MESA_SHADER_COMPUTE) {
/* We need this info for some stages even when the shader doesn't exist. */
pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(
pipeline, i, device->physical_device->rad_info.chip_class);
pipeline, i, device->physical_device->rad_info.gfx_level);
if (shader_exists)
pipeline->need_indirect_descriptor_sets |=
@@ -6663,7 +6666,7 @@ radv_graphics_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *
struct radv_depth_stencil_state ds_state =
radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
if (pipeline->device->physical_device->rad_info.gfx_level >= GFX10_3)
gfx103_pipeline_init_vrs_state(pipeline, pCreateInfo);
/* Ensure that some export memory is always allocated, for two reasons:
@@ -6682,8 +6685,7 @@ radv_graphics_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *
* instructions if any are present.
*/
struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
ps->info.ps.can_discard) &&
if ((pipeline->device->physical_device->rad_info.gfx_level <= GFX9 || ps->info.ps.can_discard) &&
!blend.spi_shader_col_format) {
if (!ps->info.ps.writes_z && !ps->info.ps.writes_stencil && !ps->info.ps.writes_sample_mask)
blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
@@ -6867,7 +6869,7 @@ radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs, const struct radv_pipelin
radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
radeon_emit(cs, shader->config.rsrc1);
radeon_emit(cs, shader->config.rsrc2);
if (device->physical_device->rad_info.chip_class >= GFX10) {
if (device->physical_device->rad_info.gfx_level >= GFX10) {
radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3);
}
}
@@ -6887,7 +6889,7 @@ radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs, const struct radv
shader->info.cs.block_size[0] * shader->info.cs.block_size[1] * shader->info.cs.block_size[2];
waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup, shader->info.wave_size);
if (device->physical_device->rad_info.chip_class >= GFX10 && waves_per_threadgroup == 1)
if (device->physical_device->rad_info.gfx_level >= GFX10 && waves_per_threadgroup == 1)
threadgroups_per_cu = 2;
radeon_set_sh_reg(
@@ -6907,7 +6909,7 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline)
struct radv_device *device = pipeline->device;
struct radeon_cmdbuf *cs = &pipeline->cs;
cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16;
cs->max_dw = device->physical_device->rad_info.gfx_level >= GFX10 ? 19 : 16;
cs->buf = malloc(cs->max_dw * 4);
radv_pipeline_generate_hw_cs(cs, pipeline);
@@ -6979,7 +6981,7 @@ radv_compute_pipeline_create(VkDevice _device, VkPipelineCache _cache,
}
pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(
pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.gfx_level);
pipeline->need_indirect_descriptor_sets |=
radv_shader_need_indirect_descriptor_sets(pipeline, MESA_SHADER_COMPUTE);
radv_pipeline_init_scratch(device, pipeline);
@@ -7184,8 +7186,8 @@ radv_GetPipelineExecutableStatisticsKHR(VkDevice _device,
struct radv_shader *shader =
radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
unsigned lds_increment = gfx_level >= GFX7 ? 512 : 256;
unsigned max_waves = radv_get_max_waves(device, shader, stage);
VkPipelineExecutableStatisticKHR *s = pStatistics;