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amd: change chip_class naming to "enum amd_gfx_level gfx_level"

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This aligns the naming with PAL.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
This commit is contained in:
Marek Olšák
2022-05-12 02:50:17 -04:00
parent 6dcf7f651f
commit 39800f0fa3
198 changed files with 2775 additions and 2776 deletions
Download Patch File Download Diff File Expand all files Collapse all files

67
src/amd/vulkan/radv_debug.c
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@@ -83,8 +83,7 @@ radv_init_trace(struct radv_device *device)
if (!device->trace_id_ptr)
return false;
ac_vm_fault_occured(device->physical_device->rad_info.chip_class, &device->dmesg_timestamp,
NULL);
ac_vm_fault_occured(device->physical_device->rad_info.gfx_level, &device->dmesg_timestamp, NULL);
return true;
}
@@ -114,7 +113,7 @@ radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
uint32_t value;
if (ws->read_registers(ws, offset, 1, &value))
ac_dump_reg(f, device->physical_device->rad_info.chip_class, offset, value, ~0);
ac_dump_reg(f, device->physical_device->rad_info.gfx_level, offset, value, ~0);
}
static void
@@ -132,7 +131,7 @@ radv_dump_debug_registers(struct radv_device *device, FILE *f)
radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
if (info->chip_class <= GFX8) {
if (info->gfx_level <= GFX8) {
radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
@@ -151,50 +150,50 @@ radv_dump_debug_registers(struct radv_device *device, FILE *f)
}
static void
radv_dump_buffer_descriptor(enum chip_class chip_class, const uint32_t *desc, FILE *f)
radv_dump_buffer_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f)
{
fprintf(f, COLOR_CYAN " Buffer:" COLOR_RESET "\n");
for (unsigned j = 0; j < 4; j++)
ac_dump_reg(f, chip_class, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, desc[j], 0xffffffff);
ac_dump_reg(f, gfx_level, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, desc[j], 0xffffffff);
}
static void
radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc, FILE *f)
radv_dump_image_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f)
{
unsigned sq_img_rsrc_word0 =
chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0;
gfx_level >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0;
fprintf(f, COLOR_CYAN " Image:" COLOR_RESET "\n");
for (unsigned j = 0; j < 8; j++)
ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4, desc[j], 0xffffffff);
ac_dump_reg(f, gfx_level, sq_img_rsrc_word0 + j * 4, desc[j], 0xffffffff);
fprintf(f, COLOR_CYAN " FMASK:" COLOR_RESET "\n");
for (unsigned j = 0; j < 8; j++)
ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4, desc[8 + j], 0xffffffff);
ac_dump_reg(f, gfx_level, sq_img_rsrc_word0 + j * 4, desc[8 + j], 0xffffffff);
}
static void
radv_dump_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc, FILE *f)
radv_dump_sampler_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f)
{
fprintf(f, COLOR_CYAN " Sampler state:" COLOR_RESET "\n");
for (unsigned j = 0; j < 4; j++) {
ac_dump_reg(f, chip_class, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, desc[j], 0xffffffff);
ac_dump_reg(f, gfx_level, R_008F30_SQ_IMG_SAMP_WORD0 + j * 4, desc[j], 0xffffffff);
}
}
static void
radv_dump_combined_image_sampler_descriptor(enum chip_class chip_class, const uint32_t *desc,
radv_dump_combined_image_sampler_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc,
FILE *f)
{
radv_dump_image_descriptor(chip_class, desc, f);
radv_dump_sampler_descriptor(chip_class, desc + 16, f);
radv_dump_image_descriptor(gfx_level, desc, f);
radv_dump_sampler_descriptor(gfx_level, desc + 16, f);
}
static void
radv_dump_descriptor_set(struct radv_device *device, struct radv_descriptor_set *set, unsigned id,
FILE *f)
{
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
const struct radv_descriptor_set_layout *layout;
int i;
@@ -210,18 +209,18 @@ radv_dump_descriptor_set(struct radv_device *device, struct radv_descriptor_set
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
radv_dump_buffer_descriptor(chip_class, desc, f);
radv_dump_buffer_descriptor(gfx_level, desc, f);
break;
case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
radv_dump_image_descriptor(chip_class, desc, f);
radv_dump_image_descriptor(gfx_level, desc, f);
break;
case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
radv_dump_combined_image_sampler_descriptor(chip_class, desc, f);
radv_dump_combined_image_sampler_descriptor(gfx_level, desc, f);
break;
case VK_DESCRIPTOR_TYPE_SAMPLER:
radv_dump_sampler_descriptor(chip_class, desc, f);
radv_dump_sampler_descriptor(gfx_level, desc, f);
break;
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
@@ -369,8 +368,8 @@ radv_dump_annotated_shaders(struct radv_pipeline *pipeline, VkShaderStageFlagBit
FILE *f)
{
struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class;
unsigned num_waves = ac_get_wave_info(chip_class, waves);
enum amd_gfx_level gfx_level = pipeline->device->physical_device->rad_info.gfx_level;
unsigned num_waves = ac_get_wave_info(gfx_level, waves);
fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET "\n\n", num_waves);
@@ -640,7 +639,7 @@ radv_dump_umr_ring(struct radv_queue *queue, FILE *f)
return;
sprintf(cmd, "umr -R %s 2>&1",
device->physical_device->rad_info.chip_class >= GFX10 ? "gfx_0.0.0" : "gfx");
device->physical_device->rad_info.gfx_level >= GFX10 ? "gfx_0.0.0" : "gfx");
fprintf(f, "\nUMR GFX ring:\n\n");
radv_dump_cmd(cmd, f);
@@ -658,7 +657,7 @@ radv_dump_umr_waves(struct radv_queue *queue, FILE *f)
return;
sprintf(cmd, "umr -O bits,halt_waves -wa %s 2>&1",
device->physical_device->rad_info.chip_class >= GFX10 ? "gfx_0.0.0" : "gfx");
device->physical_device->rad_info.gfx_level >= GFX10 ? "gfx_0.0.0" : "gfx");
fprintf(f, "\nUMR GFX waves:\n\n");
radv_dump_cmd(cmd, f);
@@ -687,7 +686,7 @@ radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs)
bool hang_occurred = radv_gpu_hang_occured(queue, ring);
bool vm_fault_occurred = false;
if (queue->device->instance->debug_flags & RADV_DEBUG_VM_FAULTS)
vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.gfx_level,
&device->dmesg_timestamp, &addr);
if (!hang_occurred && !vm_fault_occurred)
return;
@@ -964,23 +963,23 @@ radv_dump_sq_hw_regs(struct radv_device *device)
struct radv_sq_hw_reg *regs = (struct radv_sq_hw_reg *)&device->tma_ptr[6];
fprintf(stderr, "\nHardware registers:\n");
if (device->physical_device->rad_info.chip_class >= GFX10) {
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_000408_SQ_WAVE_STATUS,
if (device->physical_device->rad_info.gfx_level >= GFX10) {
ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_000408_SQ_WAVE_STATUS,
regs->status, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00040C_SQ_WAVE_TRAPSTS,
ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00040C_SQ_WAVE_TRAPSTS,
regs->trap_sts, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00045C_SQ_WAVE_HW_ID1,
ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00045C_SQ_WAVE_HW_ID1,
regs->hw_id, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00041C_SQ_WAVE_IB_STS,
ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00041C_SQ_WAVE_IB_STS,
regs->ib_sts, ~0);
} else {
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_000048_SQ_WAVE_STATUS,
ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_000048_SQ_WAVE_STATUS,
regs->status, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00004C_SQ_WAVE_TRAPSTS,
ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00004C_SQ_WAVE_TRAPSTS,
regs->trap_sts, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_000050_SQ_WAVE_HW_ID,
ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_000050_SQ_WAVE_HW_ID,
regs->hw_id, ~0);
ac_dump_reg(stderr, device->physical_device->rad_info.chip_class, R_00005C_SQ_WAVE_IB_STS,
ac_dump_reg(stderr, device->physical_device->rad_info.gfx_level, R_00005C_SQ_WAVE_IB_STS,
regs->ib_sts, ~0);
}
fprintf(stderr, "\n\n");