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amd: change chip_class naming to "enum amd_gfx_level gfx_level"

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This aligns the naming with PAL.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
This commit is contained in:
Marek Olšák
2022-05-12 02:50:17 -04:00
parent 6dcf7f651f
commit 39800f0fa3
198 changed files with 2775 additions and 2776 deletions
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98
src/amd/llvm/ac_llvm_build.c
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@@ -56,14 +56,14 @@ struct ac_llvm_flow {
* The caller is responsible for initializing ctx::module and ctx::builder.
*/
void ac_llvm_context_init(struct ac_llvm_context *ctx, struct ac_llvm_compiler *compiler,
enum chip_class chip_class, enum radeon_family family,
enum amd_gfx_level gfx_level, enum radeon_family family,
const struct radeon_info *info,
enum ac_float_mode float_mode, unsigned wave_size,
unsigned ballot_mask_bits)
{
ctx->context = LLVMContextCreate();
ctx->chip_class = chip_class;
ctx->gfx_level = gfx_level;
ctx->family = family;
ctx->info = info;
ctx->wave_size = wave_size;
@@ -393,7 +393,7 @@ void ac_build_s_barrier(struct ac_llvm_context *ctx, gl_shader_stage stage)
/* GFX6 only: s_barrier isn’t needed in TCS because an entire patch always fits into
* a single wave due to a bug workaround disallowing multi-wave HS workgroups.
*/
if (ctx->chip_class == GFX6 && stage == MESA_SHADER_TESS_CTRL)
if (ctx->gfx_level == GFX6 && stage == MESA_SHADER_TESS_CTRL)
return;
ac_build_intrinsic(ctx, "llvm.amdgcn.s.barrier", ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
@@ -865,7 +865,7 @@ void ac_prepare_cube_coords(struct ac_llvm_context *ctx, bool is_deriv, bool is_
*
* Clamp the layer earlier to work around the issue.
*/
if (ctx->chip_class <= GFX8) {
if (ctx->gfx_level <= GFX8) {
LLVMValueRef ge0;
ge0 = LLVMBuildFCmp(builder, LLVMRealOGE, tmp, ctx->f32_0, "");
tmp = LLVMBuildSelect(builder, ge0, tmp, ctx->f32_0, "");
@@ -949,7 +949,7 @@ LLVMValueRef ac_build_fs_interp(struct ac_llvm_context *ctx, LLVMValueRef llvm_c
{
LLVMValueRef args[5];
if (ctx->chip_class >= GFX11) {
if (ctx->gfx_level >= GFX11) {
LLVMValueRef p;
LLVMValueRef p10;
@@ -1002,7 +1002,7 @@ LLVMValueRef ac_build_fs_interp_f16(struct ac_llvm_context *ctx, LLVMValueRef ll
{
LLVMValueRef args[6];
if (ctx->chip_class >= GFX11) {
if (ctx->gfx_level >= GFX11) {
LLVMValueRef p;
LLVMValueRef p10;
@@ -1059,7 +1059,7 @@ LLVMValueRef ac_build_fs_interp_mov(struct ac_llvm_context *ctx, LLVMValueRef pa
{
LLVMValueRef args[4];
if (ctx->chip_class >= GFX11) {
if (ctx->gfx_level >= GFX11) {
LLVMValueRef p;
args[0] = llvm_chan;
@@ -1186,12 +1186,12 @@ LLVMValueRef ac_build_load_to_sgpr_uint_wraparound(struct ac_llvm_context *ctx,
static unsigned get_load_cache_policy(struct ac_llvm_context *ctx, unsigned cache_policy)
{
return cache_policy |
(ctx->chip_class >= GFX10 && ctx->chip_class < GFX11 && cache_policy & ac_glc ? ac_dlc : 0);
(ctx->gfx_level >= GFX10 && ctx->gfx_level < GFX11 && cache_policy & ac_glc ? ac_dlc : 0);
}
static unsigned get_store_cache_policy(struct ac_llvm_context *ctx, unsigned cache_policy)
{
if (ctx->chip_class >= GFX11)
if (ctx->gfx_level >= GFX11)
cache_policy &= ~ac_glc; /* GLC has no effect on stores */
return cache_policy;
}
@@ -1239,7 +1239,7 @@ void ac_build_buffer_store_dword(struct ac_llvm_context *ctx, LLVMValueRef rsrc,
unsigned num_channels = ac_get_llvm_num_components(vdata);
/* Split 3 channel stores if unsupported. */
if (num_channels == 3 && !ac_has_vec3_support(ctx->chip_class, false)) {
if (num_channels == 3 && !ac_has_vec3_support(ctx->gfx_level, false)) {
LLVMValueRef v[3], v01, voffset2;
for (int i = 0; i < 3; i++) {
@@ -1275,13 +1275,13 @@ static LLVMValueRef ac_build_buffer_load_common(struct ac_llvm_context *ctx, LLV
args[idx++] = soffset ? soffset : ctx->i32_0;
args[idx++] = LLVMConstInt(ctx->i32, get_load_cache_policy(ctx, cache_policy), 0);
unsigned func =
!ac_has_vec3_support(ctx->chip_class, use_format) && num_channels == 3 ? 4 : num_channels;
!ac_has_vec3_support(ctx->gfx_level, use_format) && num_channels == 3 ? 4 : num_channels;
const char *indexing_kind = structurized ? "struct" : "raw";
char name[256], type_name[8];
/* D16 is only supported on gfx8+ */
assert(!use_format || (channel_type != ctx->f16 && channel_type != ctx->i16) ||
ctx->chip_class >= GFX8);
ctx->gfx_level >= GFX8);
LLVMTypeRef type = func > 1 ? LLVMVectorType(channel_type, func) : channel_type;
ac_build_type_name_for_intr(type, type_name, sizeof(type_name));
@@ -1302,7 +1302,7 @@ LLVMValueRef ac_build_buffer_load(struct ac_llvm_context *ctx, LLVMValueRef rsrc
bool can_speculate, bool allow_smem)
{
if (allow_smem && !(cache_policy & ac_slc) &&
(!(cache_policy & ac_glc) || ctx->chip_class >= GFX8)) {
(!(cache_policy & ac_glc) || ctx->gfx_level >= GFX8)) {
assert(vindex == NULL);
LLVMValueRef result[8];
@@ -1326,7 +1326,7 @@ LLVMValueRef ac_build_buffer_load(struct ac_llvm_context *ctx, LLVMValueRef rsrc
if (num_channels == 1)
return result[0];
if (num_channels == 3 && !ac_has_vec3_support(ctx->chip_class, false))
if (num_channels == 3 && !ac_has_vec3_support(ctx->gfx_level, false))
result[num_channels++] = LLVMGetUndef(ctx->f32);
return ac_build_gather_values(ctx, result, num_channels);
}
@@ -1394,10 +1394,10 @@ static LLVMValueRef ac_build_tbuffer_load(struct ac_llvm_context *ctx, LLVMValue
args[idx++] = vindex ? vindex : ctx->i32_0;
args[idx++] = voffset ? voffset : ctx->i32_0;
args[idx++] = soffset ? soffset : ctx->i32_0;
args[idx++] = LLVMConstInt(ctx->i32, ac_get_tbuffer_format(ctx->chip_class, dfmt, nfmt), 0);
args[idx++] = LLVMConstInt(ctx->i32, ac_get_tbuffer_format(ctx->gfx_level, dfmt, nfmt), 0);
args[idx++] = LLVMConstInt(ctx->i32, get_load_cache_policy(ctx, cache_policy), 0);
unsigned func =
!ac_has_vec3_support(ctx->chip_class, true) && num_channels == 3 ? 4 : num_channels;
!ac_has_vec3_support(ctx->gfx_level, true) && num_channels == 3 ? 4 : num_channels;
const char *indexing_kind = structurized ? "struct" : "raw";
char name[256], type_name[8];
@@ -1538,7 +1538,7 @@ LLVMValueRef ac_build_opencoded_load_format(struct ac_llvm_context *ctx, unsigne
}
int log_recombine = 0;
if ((ctx->chip_class == GFX6 || ctx->chip_class >= GFX10) && !known_aligned) {
if ((ctx->gfx_level == GFX6 || ctx->gfx_level >= GFX10) && !known_aligned) {
/* Avoid alignment restrictions by loading one byte at a time. */
load_num_channels <<= load_log_size;
log_recombine = load_log_size;
@@ -1976,7 +1976,7 @@ void ac_build_export(struct ac_llvm_context *ctx, struct ac_export_args *a)
args[1] = LLVMConstInt(ctx->i32, a->enabled_channels, 0);
if (a->compr) {
assert(ctx->chip_class < GFX11);
assert(ctx->gfx_level < GFX11);
args[2] = LLVMBuildBitCast(ctx->builder, a->out[0], ctx->v2i16, "");
args[3] = LLVMBuildBitCast(ctx->builder, a->out[1], ctx->v2i16, "");
@@ -2004,7 +2004,7 @@ void ac_build_export_null(struct ac_llvm_context *ctx)
args.valid_mask = 1; /* whether the EXEC mask is valid */
args.done = 1; /* DONE bit */
/* Gfx11 doesn't support null exports, and mrt0 should be exported instead. */
args.target = ctx->chip_class >= GFX11 ? V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL;
args.target = ctx->gfx_level >= GFX11 ? V_008DFC_SQ_EXP_MRT : V_008DFC_SQ_EXP_NULL;
args.compr = 0; /* COMPR flag (0 = 32-bit export) */
args.out[0] = LLVMGetUndef(ctx->f32); /* R */
args.out[1] = LLVMGetUndef(ctx->f32); /* G */
@@ -2108,11 +2108,11 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx, struct ac_image_
assert((a->bias ? 1 : 0) + (a->lod ? 1 : 0) + (a->level_zero ? 1 : 0) + (a->derivs[0] ? 1 : 0) <=
1);
assert((a->min_lod ? 1 : 0) + (a->lod ? 1 : 0) + (a->level_zero ? 1 : 0) <= 1);
assert(!a->d16 || (ctx->chip_class >= GFX8 && a->opcode != ac_image_atomic &&
assert(!a->d16 || (ctx->gfx_level >= GFX8 && a->opcode != ac_image_atomic &&
a->opcode != ac_image_atomic_cmpswap && a->opcode != ac_image_get_lod &&
a->opcode != ac_image_get_resinfo));
assert(!a->a16 || ctx->chip_class >= GFX9);
assert(a->g16 == a->a16 || ctx->chip_class >= GFX10);
assert(!a->a16 || ctx->gfx_level >= GFX9);
assert(a->g16 == a->a16 || ctx->gfx_level >= GFX10);
assert(!a->offset ||
ac_get_elem_bits(ctx, LLVMTypeOf(a->offset)) == 32);
@@ -2358,7 +2358,7 @@ LLVMValueRef ac_build_cvt_pknorm_i16_f16(struct ac_llvm_context *ctx,
LLVMTypeRef param_types[] = {ctx->f16, ctx->f16};
LLVMTypeRef calltype = LLVMFunctionType(ctx->i32, param_types, 2, false);
LLVMValueRef code = LLVMConstInlineAsm(calltype,
ctx->chip_class >= GFX11 ?
ctx->gfx_level >= GFX11 ?
"v_cvt_pk_norm_i16_f16 $0, $1, $2" :
"v_cvt_pknorm_i16_f16 $0, $1, $2",
"=v,v,v", false, false);
@@ -2371,7 +2371,7 @@ LLVMValueRef ac_build_cvt_pknorm_u16_f16(struct ac_llvm_context *ctx,
LLVMTypeRef param_types[] = {ctx->f16, ctx->f16};
LLVMTypeRef calltype = LLVMFunctionType(ctx->i32, param_types, 2, false);
LLVMValueRef code = LLVMConstInlineAsm(calltype,
ctx->chip_class >= GFX11 ?
ctx->gfx_level >= GFX11 ?
"v_cvt_pk_norm_u16_f16 $0, $1, $2" :
"v_cvt_pknorm_u16_f16 $0, $1, $2",
"=v,v,v", false, false);
@@ -2458,7 +2458,7 @@ LLVMValueRef ac_build_fmad(struct ac_llvm_context *ctx, LLVMValueRef s0, LLVMVal
LLVMValueRef s2)
{
/* FMA is better on GFX10, because it has FMA units instead of MUL-ADD units. */
if (ctx->chip_class >= GFX10) {
if (ctx->gfx_level >= GFX10) {
return ac_build_intrinsic(ctx, "llvm.fma.f32", ctx->f32, (LLVMValueRef[]){s0, s1, s2}, 3,
AC_FUNC_ATTR_READNONE);
}
@@ -2473,7 +2473,7 @@ void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned wait_flags)
unsigned expcnt = 7;
unsigned lgkmcnt = 63;
unsigned vmcnt = ctx->chip_class >= GFX9 ? 63 : 15;
unsigned vmcnt = ctx->gfx_level >= GFX9 ? 63 : 15;
unsigned vscnt = 63;
if (wait_flags & AC_WAIT_EXP)
@@ -2484,7 +2484,7 @@ void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned wait_flags)
vmcnt = 0;
if (wait_flags & AC_WAIT_VSTORE) {
if (ctx->chip_class >= GFX10)
if (ctx->gfx_level >= GFX10)
vscnt = 0;
else
vmcnt = 0;
@@ -2500,7 +2500,7 @@ void ac_build_waitcnt(struct ac_llvm_context *ctx, unsigned wait_flags)
unsigned simm16;
if (ctx->chip_class >= GFX11)
if (ctx->gfx_level >= GFX11)
simm16 = expcnt | (lgkmcnt << 4) | (vmcnt << 10);
else
simm16 = (lgkmcnt << 8) | (expcnt << 4) | (vmcnt & 0xf) | ((vmcnt >> 4) << 14);
@@ -2519,7 +2519,7 @@ LLVMValueRef ac_build_fsat(struct ac_llvm_context *ctx, LLVMValueRef src,
LLVMValueRef one = LLVMConstReal(type, 1.0);
LLVMValueRef result;
if (bitsize == 64 || (bitsize == 16 && ctx->chip_class <= GFX8) || type == ctx->v2f16) {
if (bitsize == 64 || (bitsize == 16 && ctx->gfx_level <= GFX8) || type == ctx->v2f16) {
/* Use fmin/fmax for 64-bit fsat or 16-bit on GFX6-GFX8 because LLVM
* doesn't expose an intrinsic.
*/
@@ -2547,7 +2547,7 @@ LLVMValueRef ac_build_fsat(struct ac_llvm_context *ctx, LLVMValueRef src,
AC_FUNC_ATTR_READNONE);
}
if (ctx->chip_class < GFX9 && bitsize == 32) {
if (ctx->gfx_level < GFX9 && bitsize == 32) {
/* Only pre-GFX9 chips do not flush denorms. */
result = ac_build_canonicalize(ctx, result, bitsize);
}
@@ -2741,7 +2741,7 @@ void ac_init_exec_full_mask(struct ac_llvm_context *ctx)
void ac_declare_lds_as_pointer(struct ac_llvm_context *ctx)
{
unsigned lds_size = ctx->chip_class >= GFX7 ? 65536 : 32768;
unsigned lds_size = ctx->gfx_level >= GFX7 ? 65536 : 32768;
ctx->lds = LLVMBuildIntToPtr(
ctx->builder, ctx->i32_0,
LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), AC_ADDR_SPACE_LDS), "lds");
@@ -3642,7 +3642,7 @@ static LLVMValueRef ac_build_alu_op(struct ac_llvm_context *ctx, LLVMValueRef lh
static LLVMValueRef ac_wavefront_shift_right_1(struct ac_llvm_context *ctx, LLVMValueRef src,
LLVMValueRef identity, unsigned maxprefix)
{
if (ctx->chip_class >= GFX10) {
if (ctx->gfx_level >= GFX10) {
/* wavefront shift_right by 1 on GFX10 (emulate dpp_wf_sr1) */
LLVMValueRef active, tmp1, tmp2;
LLVMValueRef tid = ac_get_thread_id(ctx);
@@ -3672,7 +3672,7 @@ static LLVMValueRef ac_wavefront_shift_right_1(struct ac_llvm_context *ctx, LLVM
return LLVMBuildSelect(ctx->builder, active, tmp2, tmp1, "");
}
} else if (ctx->chip_class >= GFX8) {
} else if (ctx->gfx_level >= GFX8) {
return ac_build_dpp(ctx, identity, src, dpp_wf_sr1, 0xf, 0xf, false);
}
@@ -3716,7 +3716,7 @@ static LLVMValueRef ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMVa
result = src;
if (ctx->chip_class <= GFX7) {
if (ctx->gfx_level <= GFX7) {
assert(maxprefix == 64);
LLVMValueRef tid = ac_get_thread_id(ctx);
LLVMValueRef active;
@@ -3781,7 +3781,7 @@ static LLVMValueRef ac_build_scan(struct ac_llvm_context *ctx, nir_op op, LLVMVa
if (maxprefix <= 16)
return result;
if (ctx->chip_class >= GFX10) {
if (ctx->gfx_level >= GFX10) {
LLVMValueRef tid = ac_get_thread_id(ctx);
LLVMValueRef active;
@@ -3882,7 +3882,7 @@ LLVMValueRef ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_
if (cluster_size == 4)
return ac_build_wwm(ctx, result);
if (ctx->chip_class >= GFX8)
if (ctx->gfx_level >= GFX8)
swap = ac_build_dpp(ctx, identity, result, dpp_row_half_mirror, 0xf, 0xf, false);
else
swap = ac_build_ds_swizzle(ctx, result, ds_pattern_bitmode(0x1f, 0, 0x04));
@@ -3890,7 +3890,7 @@ LLVMValueRef ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_
if (cluster_size == 8)
return ac_build_wwm(ctx, result);
if (ctx->chip_class >= GFX8)
if (ctx->gfx_level >= GFX8)
swap = ac_build_dpp(ctx, identity, result, dpp_row_mirror, 0xf, 0xf, false);
else
swap = ac_build_ds_swizzle(ctx, result, ds_pattern_bitmode(0x1f, 0, 0x08));
@@ -3898,9 +3898,9 @@ LLVMValueRef ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_
if (cluster_size == 16)
return ac_build_wwm(ctx, result);
if (ctx->chip_class >= GFX10)
if (ctx->gfx_level >= GFX10)
swap = ac_build_permlane16(ctx, result, 0, true, false);
else if (ctx->chip_class >= GFX8 && cluster_size != 32)
else if (ctx->gfx_level >= GFX8 && cluster_size != 32)
swap = ac_build_dpp(ctx, identity, result, dpp_row_bcast15, 0xa, 0xf, false);
else
swap = ac_build_ds_swizzle(ctx, result, ds_pattern_bitmode(0x1f, 0, 0x10));
@@ -3908,9 +3908,9 @@ LLVMValueRef ac_build_reduce(struct ac_llvm_context *ctx, LLVMValueRef src, nir_
if (cluster_size == 32)
return ac_build_wwm(ctx, result);
if (ctx->chip_class >= GFX8) {
if (ctx->gfx_level >= GFX8) {
if (ctx->wave_size == 64) {
if (ctx->chip_class >= GFX10)
if (ctx->gfx_level >= GFX10)
swap = ac_build_readlane(ctx, result, LLVMConstInt(ctx->i32, 31, false));
else
swap = ac_build_dpp(ctx, identity, result, dpp_row_bcast31, 0xc, 0xf, false);
@@ -4134,7 +4134,7 @@ void ac_build_dual_src_blend_swizzle(struct ac_llvm_context *ctx,
struct ac_export_args *mrt0,
struct ac_export_args *mrt1)
{
assert(ctx->chip_class >= GFX11);
assert(ctx->gfx_level >= GFX11);
assert(mrt0->enabled_channels == mrt1->enabled_channels);
for (int i = 0; i < 4; i++) {
@@ -4147,7 +4147,7 @@ LLVMValueRef ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src
unsigned lane1, unsigned lane2, unsigned lane3)
{
unsigned mask = dpp_quad_perm(lane0, lane1, lane2, lane3);
if (ctx->chip_class >= GFX8) {
if (ctx->gfx_level >= GFX8) {
return ac_build_dpp(ctx, src, src, mask, 0xf, 0xf, false);
} else {
return ac_build_ds_swizzle(ctx, src, (1 << 15) | mask);
@@ -4316,23 +4316,23 @@ void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueR
if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
assert(!depth);
args->compr = ctx->chip_class < GFX11; /* COMPR flag */
args->compr = ctx->gfx_level < GFX11; /* COMPR flag */
if (stencil) {
/* Stencil should be in X[23:16]. */
stencil = ac_to_integer(ctx, stencil);
stencil = LLVMBuildShl(ctx->builder, stencil, LLVMConstInt(ctx->i32, 16, 0), "");
args->out[0] = ac_to_float(ctx, stencil);
mask |= ctx->chip_class >= GFX11 ? 0x1 : 0x3;
mask |= ctx->gfx_level >= GFX11 ? 0x1 : 0x3;
}
if (samplemask) {
/* SampleMask should be in Y[15:0]. */
args->out[1] = samplemask;
mask |= ctx->chip_class >= GFX11 ? 0x2 : 0xc;
mask |= ctx->gfx_level >= GFX11 ? 0x2 : 0xc;
}
if (mrtz_alpha) {
/* MRT0 alpha should be in Y[31:16] if alpha-to-coverage is enabled and MRTZ is present. */
assert(ctx->chip_class >= GFX11);
assert(ctx->gfx_level >= GFX11);
mrtz_alpha = LLVMBuildFPTrunc(ctx->builder, mrtz_alpha, ctx->f16, "");
mrtz_alpha = ac_to_integer(ctx, mrtz_alpha);
mrtz_alpha = LLVMBuildZExt(ctx->builder, mrtz_alpha, ctx->i32, "");
@@ -4362,7 +4362,7 @@ void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueR
/* GFX6 (except OLAND and HAINAN) has a bug that it only looks
* at the X writemask component. */
if (ctx->chip_class == GFX6 && ctx->family != CHIP_OLAND && ctx->family != CHIP_HAINAN)
if (ctx->gfx_level == GFX6 && ctx->family != CHIP_OLAND && ctx->family != CHIP_HAINAN)
mask |= 0x1;
/* Specify which components to enable */
@@ -4385,7 +4385,7 @@ void ac_build_sendmsg_gs_alloc_req(struct ac_llvm_context *ctx, LLVMValueRef wav
* We always have to export at least 1 primitive.
* Export a degenerate triangle using vertex 0 for all 3 vertices.
*/
if (prim_cnt == ctx->i32_0 && ctx->chip_class == GFX10) {
if (prim_cnt == ctx->i32_0 && ctx->gfx_level == GFX10) {
assert(vtx_cnt == ctx->i32_0);
prim_cnt = ctx->i32_1;
vtx_cnt = ctx->i32_1;