intel: Implement Gen12 workaround for array textures of size 1
Gen12 does not support RENDER_SURFACE_STATE::SurfaceArray = true && RENDER_SURFACE_STATE::Depth = 0. SurfaceArray can only be set to true if Depth >= 1. We workaround this limitation by adding the max(value, 1) snippet in the shaders on the 3 components for texture array sizes. Tested on Gen9 with the following Vulkan CTS tests : dEQP-VK.image.image_size.2d_array.* v2: Drop debug print (Tapani) Switch to GEN:BUG instead of Wa_ v3: Fix dEQP-VK.image.image_size.1d_array.* cases (Lionel) v4: Fix dEQP-VK.glsl.texture_functions.query.texturesize.* cases (Missing tex_op handling) (Lionel) v5: Missing break statement (Lionel) v6: Fixup comment (Tapani) v7: Fixup comment again (Tapani) v8: Don't use sample_dim as index (Jason) Rename pass Simplify control flow Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v7) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362>
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@@ -84,6 +84,7 @@ COMPILER_FILES = \
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compiler/brw_nir.c \
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compiler/brw_nir.c \
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compiler/brw_nir_analyze_boolean_resolves.c \
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compiler/brw_nir_analyze_boolean_resolves.c \
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compiler/brw_nir_analyze_ubo_ranges.c \
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compiler/brw_nir_analyze_ubo_ranges.c \
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compiler/brw_nir_clamp_image_1d_2d_array_sizes.c \
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compiler/brw_nir_attribute_workarounds.c \
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compiler/brw_nir_attribute_workarounds.c \
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compiler/brw_nir_lower_alpha_to_coverage.c \
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compiler/brw_nir_lower_alpha_to_coverage.c \
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compiler/brw_nir_lower_conversions.c \
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compiler/brw_nir_lower_conversions.c \
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@@ -665,6 +665,9 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
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!(devinfo->gen >= 10 || devinfo->is_kabylake))
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!(devinfo->gen >= 10 || devinfo->is_kabylake))
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OPT(brw_nir_apply_trig_workarounds);
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OPT(brw_nir_apply_trig_workarounds);
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if (devinfo->gen >= 12)
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OPT(brw_nir_clamp_image_1d_2d_array_sizes);
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static const nir_lower_tex_options tex_options = {
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static const nir_lower_tex_options tex_options = {
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.lower_txp = ~0,
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.lower_txp = ~0,
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.lower_txf_offset = true,
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.lower_txf_offset = true,
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@@ -134,6 +134,8 @@ void brw_postprocess_nir(nir_shader *nir,
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const struct brw_compiler *compiler,
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const struct brw_compiler *compiler,
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bool is_scalar);
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bool is_scalar);
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bool brw_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader);
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bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
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bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
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const uint8_t *attrib_wa_flags);
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const uint8_t *attrib_wa_flags);
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139
src/intel/compiler/brw_nir_clamp_image_1d_2d_array_sizes.c
Normal file
139
src/intel/compiler/brw_nir_clamp_image_1d_2d_array_sizes.c
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@@ -0,0 +1,139 @@
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/*
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* Copyright © 2020 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "compiler/nir/nir_builder.h"
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#include "brw_nir.h"
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/**
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* GEN:BUG:1806565034:
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*
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* Gen12+ allows to set RENDER_SURFACE_STATE::SurfaceArray to 1 only if
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* array_len > 1. Setting RENDER_SURFACE_STATE::SurfaceArray to 0 results in
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* the HW RESINFO message to report an array size of 0 which breaks texture
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* array size queries.
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*
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* This NIR pass works around this by patching the array size with a
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* MAX(array_size, 1) for array textures.
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*/
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bool
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brw_nir_clamp_image_1d_2d_array_sizes(nir_shader *shader)
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{
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bool progress = false;
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nir_builder b;
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nir_foreach_function(func, shader) {
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bool function_progress = false;
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if (!func->impl)
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continue;
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nir_builder_init(&b, func->impl);
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nir_foreach_block(block, func->impl) {
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nir_foreach_instr_safe(instr, block) {
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nir_ssa_def *image_size = NULL;
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switch (instr->type) {
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_image_size:
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case nir_intrinsic_bindless_image_size:
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if (!nir_intrinsic_image_array(intr))
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break;
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image_size = &intr->dest.ssa;
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break;
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case nir_intrinsic_image_deref_size: {
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nir_deref_instr *deref = nir_src_as_deref(intr->src[0]);
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assert(glsl_type_is_image(deref->type));
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if (!glsl_sampler_type_is_array(deref->type))
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break;
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image_size = &intr->dest.ssa;
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break;
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}
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default:
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break;
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}
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break;
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}
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case nir_instr_type_tex: {
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nir_tex_instr *tex_instr = nir_instr_as_tex(instr);
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if (tex_instr->op != nir_texop_txs)
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break;
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if (!tex_instr->is_array)
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break;
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image_size = &tex_instr->dest.ssa;
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break;
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}
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default:
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break;
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}
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if (!image_size)
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continue;
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b.cursor = nir_after_instr(instr);
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nir_ssa_def *components[4];
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for (int i = 0; i < image_size->num_components; i++) {
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if (i == (image_size->num_components - 1)) {
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components[i] = nir_imax(&b, nir_channel(&b, image_size, i),
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nir_imm_int(&b, 1));
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} else {
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components[i] = nir_channel(&b, image_size, i);
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}
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}
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nir_ssa_def *image_size_replacement =
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nir_vec(&b, components, image_size->num_components);
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b.cursor = nir_after_instr(instr);
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nir_ssa_def_rewrite_uses_after(image_size,
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nir_src_for_ssa(image_size_replacement),
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image_size_replacement->parent_instr);
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function_progress = true;
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}
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}
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if (function_progress) {
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nir_metadata_preserve(func->impl, nir_metadata_block_index |
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nir_metadata_dominance);
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progress = function_progress;
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}
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}
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return progress;
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}
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@@ -83,6 +83,7 @@ libintel_compiler_files = files(
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'brw_nir_lower_mem_access_bit_sizes.c',
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'brw_nir_lower_mem_access_bit_sizes.c',
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'brw_nir_opt_peephole_ffma.c',
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'brw_nir_opt_peephole_ffma.c',
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'brw_nir_tcs_workarounds.c',
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'brw_nir_tcs_workarounds.c',
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'brw_nir_clamp_image_1d_2d_array_sizes.c',
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'brw_packed_float.c',
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'brw_packed_float.c',
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'brw_predicated_break.cpp',
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'brw_predicated_break.cpp',
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'brw_reg.h',
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'brw_reg.h',
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@@ -402,7 +402,11 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
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unreachable("bad SurfaceType");
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unreachable("bad SurfaceType");
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}
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}
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#if GEN_GEN >= 7
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#if GEN_GEN >= 12
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/* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
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s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
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info->view->array_len > 1;
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#elif GEN_GEN >= 7
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s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
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s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
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#endif
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#endif
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