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intel: Implement Gen12 workaround for array textures of size 1

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Gen12 does not support RENDER_SURFACE_STATE::SurfaceArray = true &&
RENDER_SURFACE_STATE::Depth = 0. SurfaceArray can only be set to true
if Depth >= 1.

We workaround this limitation by adding the max(value, 1) snippet in
the shaders on the 3 components for texture array sizes.

Tested on Gen9 with the following Vulkan CTS tests :
dEQP-VK.image.image_size.2d_array.*

v2: Drop debug print (Tapani)
    Switch to GEN:BUG instead of Wa_

v3: Fix dEQP-VK.image.image_size.1d_array.* cases (Lionel)

v4: Fix dEQP-VK.glsl.texture_functions.query.texturesize.* cases
    (Missing tex_op handling) (Lionel)

v5: Missing break statement (Lionel)

v6: Fixup comment (Tapani)

v7: Fixup comment again (Tapani)

v8: Don't use sample_dim as index (Jason)
    Rename pass
    Simplify control flow

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v7)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3362>
This commit is contained in:
Lionel Landwerlin
2020-01-13 15:11:25 +02:00
parent 4d03e53127
commit 397ff2976b
6 changed files with 151 additions and 1 deletions
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1
src/intel/compiler/meson.build
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@@ -83,6 +83,7 @@ libintel_compiler_files = files(
'brw_nir_lower_mem_access_bit_sizes.c',
'brw_nir_opt_peephole_ffma.c',
'brw_nir_tcs_workarounds.c',
'brw_nir_clamp_image_1d_2d_array_sizes.c',
'brw_packed_float.c',
'brw_predicated_break.cpp',
'brw_reg.h',