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radv, aco: Add uses_full_subgroups to compute shader info.

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Allow the compiler to assume that the shader always has full subgroups,
meaning that the initial EXEC mask is -1 in all waves (all lanes enabled).
This assumption is incorrect for ray tracing and internal (meta) shaders
because they can use unaligned dispatch.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20670>
This commit is contained in:
Timur Kristóf
2023-01-10 12:58:52 +01:00
committed by Marge Bot
parent 22b350fa27
commit 39448c8e9c
6 changed files with 17 additions and 1 deletions
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3
src/amd/vulkan/radv_pipeline.c
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@@ -2471,6 +2471,7 @@ radv_fill_shader_info(struct radv_pipeline *pipeline,
radv_nir_shader_info_init(&stages[i].info);
radv_nir_shader_info_pass(device, stages[i].nir, pipeline_layout, pipeline_key,
pipeline->type,
&stages[i].info);
}
@@ -2998,7 +2999,7 @@ radv_pipeline_create_gs_copy_shader(struct radv_pipeline *pipeline,
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
struct radv_shader_info info = {0};
radv_nir_shader_info_pass(device, nir, pipeline_layout, pipeline_key, &info);
radv_nir_shader_info_pass(device, nir, pipeline_layout, pipeline_key, pipeline->type, &info);
info.wave_size = 64; /* Wave32 not supported. */
info.workgroup_size = 64; /* HW VS: separate waves, no workgroups */
info.so = gs_info->so;