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amd/registers: fix fields conflict detection

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The existing code handled the case where the new definition of the
same field was larger than the old one.
This commit adds a check to handle the reverse case: the new def
is smaller than the old one (= so writing using the merged macro
would affect the next fields).

The affected fields are:
* LGKM_CNT (in SQ_WAVE_IB_STS)
* DONUT_SPLIT (in VGT_TESS_DISTRIBUTION)
* HEAD_QUEUE (in GDS_GWS_RESOURCE)

DONUT_SPLIT is the only one used by radeonsi/radv.

Fixes: e6184b0892 ("amd/registers: scripts for processing register descriptions in JSON")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12063>
This commit is contained in:
Pierre-Eric Pelloux-Prayer
2021-07-26 10:47:20 +02:00
committed by Marge Bot
parent 2ea88d7cea
commit 3914bd457b
3 changed files with 23 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/amd/vulkan/si_cmd_buffer.c
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@@ -503,13 +503,13 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
if (physical_device->rad_info.chip_class >= GFX9) {
radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) |
S_028B50_ACCUM_QUAD(24) | S_028B50_DONUT_SPLIT(24) |
S_028B50_ACCUM_QUAD(24) | S_028B50_DONUT_SPLIT_GFX9(24) |
S_028B50_TRAP_SPLIT(6));
} else if (physical_device->rad_info.chip_class >= GFX8) {
uint32_t vgt_tess_distribution;
vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) |
S_028B50_ACCUM_QUAD(11) | S_028B50_DONUT_SPLIT(16);
S_028B50_ACCUM_QUAD(11) | S_028B50_DONUT_SPLIT_GFX81(16);
if (physical_device->rad_info.family == CHIP_FIJI ||
physical_device->rad_info.family >= CHIP_POLARIS10)