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nir: Add tessellation related AMD-specific intrinsics.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9201>
This commit is contained in:
Timur Kristóf
2021-02-15 22:01:02 +01:00
committed by Marge Bot
parent 744dc74078
commit 38df949f98
3 changed files with 23 additions and 0 deletions
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6
src/compiler/nir/nir_divergence_analysis.c
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@@ -136,6 +136,11 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_load_line_width:
case nir_intrinsic_load_aa_line_width:
case nir_intrinsic_load_fb_layers_v3d:
case nir_intrinsic_load_tcs_num_patches_amd:
case nir_intrinsic_load_ring_tess_factors_amd:
case nir_intrinsic_load_ring_tess_offchip_amd:
case nir_intrinsic_load_ring_tess_factors_offset_amd:
case nir_intrinsic_load_ring_tess_offchip_offset_amd:
is_divergent = false;
break;
@@ -473,6 +478,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr)
case nir_intrinsic_mbcnt_amd:
case nir_intrinsic_elect:
case nir_intrinsic_load_tlb_color_v3d:
case nir_intrinsic_load_tess_rel_patch_id_amd:
is_divergent = true;
break;

12
src/compiler/nir/nir_intrinsics.py
View File

@@ -1141,6 +1141,18 @@ intrinsic("load_buffer_amd", src_comp=[4, 1, 1], dest_comp=0, indices=[BASE, IS_
# src[] = { store value, descriptor, base address, scalar offset }
intrinsic("store_buffer_amd", src_comp=[0, 4, 1, 1], indices=[BASE, WRITE_MASK, IS_SWIZZLED, SLC_AMD, MEMORY_MODES])
# Descriptor where TCS outputs are stored for TES
system_value("ring_tess_offchip_amd", 4)
system_value("ring_tess_offchip_offset_amd", 1)
# Descriptor where TCS outputs are stored for the HW tessellator
system_value("ring_tess_factors_amd", 4)
system_value("ring_tess_factors_offset_amd", 1)
# Number of patches processed by each TCS workgroup
system_value("tcs_num_patches_amd", 1)
# Relative tessellation patch ID within the current workgroup
system_value("tess_rel_patch_id_amd", 1)
# V3D-specific instrinc for tile buffer color reads.
#
# The hardware requires that we read the samples and components of a pixel

5
src/compiler/nir/nir_range_analysis.c
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@@ -1388,6 +1388,11 @@ nir_unsigned_upper_bound(nir_shader *shader, struct hash_table *range_ht,
res = MAX2(src0, src1);
break;
}
case nir_intrinsic_load_tess_rel_patch_id_amd:
case nir_intrinsic_load_tcs_num_patches_amd:
/* Very generous maximum: TCS/TES executed by largest possible workgroup */
res = config->max_work_group_invocations / MAX2(shader->info.tess.tcs_vertices_out, 1u);
break;
default:
break;
}