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anv/blorp: Split blorp_exec into a render and compute

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And set the relevant push_constants_dirty for each case.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14275>
This commit is contained in:
Caio Oliveira
2021-12-21 00:36:10 -08:00
committed by Marge Bot
parent 2686c5419d
commit 37fca614b8
1 changed files with 55 additions and 32 deletions
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87
src/intel/vulkan/genX_blorp_exec.c
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@@ -249,21 +249,14 @@ blorp_get_l3_config(struct blorp_batch *batch)
return cmd_buffer->state.current_l3_config;
}
void
genX(blorp_exec)(struct blorp_batch *batch,
const struct blorp_params *params)
static void
blorp_exec_on_render(struct blorp_batch *batch,
const struct blorp_params *params)
{
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
if (batch->flags & BLORP_BATCH_USE_COMPUTE)
assert(cmd_buffer->pool->queue_family->queueFlags & VK_QUEUE_COMPUTE_BIT);
else
assert(cmd_buffer->pool->queue_family->queueFlags & VK_QUEUE_GRAPHICS_BIT);
assert((batch->flags & BLORP_BATCH_USE_COMPUTE) == 0);
if (!cmd_buffer->state.current_l3_config) {
const struct intel_l3_config *cfg =
intel_get_default_l3_config(&cmd_buffer->device->info);
genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
}
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
assert(cmd_buffer->pool->queue_family->queueFlags & VK_QUEUE_GRAPHICS_BIT);
const unsigned scale = params->fast_clear_op ? UINT_MAX : 1;
genX(cmd_buffer_emit_hashing_mode)(cmd_buffer, params->x1 - params->x0,
@@ -288,25 +281,8 @@ genX(blorp_exec)(struct blorp_batch *batch,
!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
genX(cmd_buffer_emit_gfx12_depth_wa)(cmd_buffer, &params->depth.surf);
#if GFX_VER == 7
/* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
* indirect fast-clear colors can cause GPU hangs if we don't stall first.
* See genX(cmd_buffer_mi_memcpy) for more details.
*/
if (params->src.clear_color_addr.buffer ||
params->dst.clear_color_addr.buffer) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_CS_STALL_BIT,
"before blorp prep fast clear");
}
#endif
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
if (batch->flags & BLORP_BATCH_USE_COMPUTE)
genX(flush_pipeline_select_gpgpu)(cmd_buffer);
else
genX(flush_pipeline_select_3d)(cmd_buffer);
genX(flush_pipeline_select_3d)(cmd_buffer);
genX(cmd_buffer_emit_gfx7_depth_flush)(cmd_buffer);
@@ -352,5 +328,52 @@ genX(blorp_exec)(struct blorp_batch *batch,
cmd_buffer->state.gfx.vb_dirty = ~0;
cmd_buffer->state.gfx.dirty |= ~skip_bits;
cmd_buffer->state.push_constants_dirty = ~0;
cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_ALL_GRAPHICS;
}
static void
blorp_exec_on_compute(struct blorp_batch *batch,
const struct blorp_params *params)
{
assert(batch->flags & BLORP_BATCH_USE_COMPUTE);
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
assert(cmd_buffer->pool->queue_family->queueFlags & VK_QUEUE_COMPUTE_BIT);
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
genX(flush_pipeline_select_gpgpu)(cmd_buffer);
blorp_exec(batch, params);
cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
}
void
genX(blorp_exec)(struct blorp_batch *batch,
const struct blorp_params *params)
{
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
if (!cmd_buffer->state.current_l3_config) {
const struct intel_l3_config *cfg =
intel_get_default_l3_config(&cmd_buffer->device->info);
genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
}
#if GFX_VER == 7
/* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
* indirect fast-clear colors can cause GPU hangs if we don't stall first.
* See genX(cmd_buffer_mi_memcpy) for more details.
*/
if (params->src.clear_color_addr.buffer ||
params->dst.clear_color_addr.buffer) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_CS_STALL_BIT,
"before blorp prep fast clear");
}
#endif
if (batch->flags & BLORP_BATCH_USE_COMPUTE)
blorp_exec_on_compute(batch, params);
else
blorp_exec_on_render(batch, params);
}